Patent Application
20240118492
In the past, conventional fabrication of silicon and silicon dioxide (silica) optical waveguides traditionally relied on high temperatures that exceeded 1000° C. Such high temperatures damaged or weakened microelectronic devices. Conventional waveguides based on silicon and silicon dioxide also required a light-bending radius that was too large to include such optoelectronic circuits on small electronic dies and chips. Ongoing efforts aim to fully integrate silicon photonics with conventional microelectronics in unified packages, where optical interconnects provide faster data transfer between dies and microchips, and also faster data transfer within the dies and chips themselves.
Silicon, as a good conductor of infrared light, has become important to optoelectronics and provides many technical and economic advantages. Silicon photonics can combine the advantages of photonics with the widespread use of silicon in conventional CMOS manufacturing. Photonics offers high-performance communication, low power of operation, and small size and weight. CMOS offers volume production, low cost, miniaturization, and high integration. Silicon photonics therefore provides high integration, miniaturization, higher bandwidth, lower cost, and lower power of operation. Micro-optoelectronic integration using silicon photonics also cuts the cost of optical links.
Compound semiconductors for optoelectronics and silicon photonics combine an element from group III of the periodic table (e.g., In, Ga, Al) with an element from group V of the periodic table (e.g., As, P, Sb, N). This yields twelve different III-V compounds, but the most commercially useful of these are currently GaAs, InP, GaN, and GaP. On a silicon substrate it is very difficult to epitaxially grow quality III-V semiconductor materials needed for mass-produced construction of photonic devices. Fabrication procedures such as etching are completely different from silicon processes. Moreover, contamination from III-V semiconductors must be completely prevented from contact or inclusion with the silicon of silicon electronics. Thus, it is difficult to introduce III-V semiconductor compounds into silicon electronics. Polymer waveguides of organic compounds cause less damage to electronic devices, but they are limited to the uppermost layers available only after electronic circuits have been completed, or to other locations isolated from the electronic devices being fabricated because they cannot withstand the high temperatures present in electronic device fabrication.
Silicon photonic circuits most often operate in the infrared at a wavelength of 1550 nanometers, at which silicon becomes a good conduit for transmission of the infrared optical beams. A top and bottom cladding of silicon dioxide (silica) on a waveguide structure made of silicon confines the infrared light within the silicon due to differences in the refraction indices of silicon and silicon dioxide, similar in some respects to how light is conducted in a fiber optic filament. Silicon photonic devices that use such silicon waveguides can be constructed by semiconductor fabrication techniques previously used exclusively for microelectronics. Since silicon is already used as the substrate in most conventional integrated circuits for microelectronics, hybrid devices in which the optical and electronic components are integrated onto a single microchip can be made with conventional semiconductor fabrication processes, sometimes even without retooling.
Processes that fabricate photonic devices using silicon and silicon dioxide can also utilize conventional silicon on insulator (SOI) techniques that are already well-known in microelectronics, providing a SOI waveguide layer on a wafer, to which optical dies such as LEDs, lasers, and photodetectors may be conventionally attached by less-than-ideal means.
Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperature photonics processes destroying the microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for a silicon photonics-microelectronics package when two wafers are joined.
This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.
Certain embodiments of the disclosure will hereafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements. It should be understood, however, that the accompanying figures illustrate the various implementations described herein and are not meant to limit the scope of various technologies described herein.
This disclosure describes integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects. Example processes and apparatuses described herein provide various ways of using direct bonding techniques to create integrated optical waveguides, direct-bonded waveguide interface joints, photonic wire, and chip-to-chip optical routing. Optical transmission and routing terms and phrases, such as “optical conduit,” “optical trace,” “waveguide,” “photonic wire,” “optical circuit,” and component parts of these, may be used somewhat interchangeably herein, depending on context.
An example optical interconnect joins first and second optical conduits. A first direct oxide bond performed at room temperature joins outer claddings of the two optical conduits, and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature, for example. The second direct bonding of the inner cores is formed during an annealing process due to the differential in coefficients of thermal expansion between the outer cladding and the inner core of each optical conduit being joined. These two low-temperature bonds allow photonics processes to be applied in a single integrated circuit or microelectronics package without conventional high-temperature photonics processes destroying the microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces with no gaps or minimal gaps in the interface between surfaces, and no detrimental extra layers added to make the interface, provide better matching with rectangular waveguides and provide better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for a silicon photonics-microelectronics package when two wafers are joined.
The example integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects described herein provide nano-small geometrical structures for compatibility with silicon electronics, so that very small optoelectronics packages may be produced.
The example integrated waveguides described herein can accommodate passive and dynamic photonic devices, wavelength filters, modulators, as well as compatibility with light emission functions, and light detection functions with low propagation loss.
The example optical waveguides used as photonic routing can have nano-small core dimensions and micrometer-scale bending sections to match the scale of microelectronic circuits. The example waveguides can be constructed on silicon-on-insulator (SOI) substrates, where the uppermost silicon layer of the SOI substrate is employed as the waveguide core, eliminating the need to specially form the core material. The cladding material can be silica-based compounds like silicon dioxide, formed by low-temperature processes, plasma-enhanced chemical vapor deposition, and so forth. Bonding between materials at the example optical interfaces can be performed by low-temperature DBI or ZIBOND direct bonding processes (Xperi Corporation, San Jose, CA). These features result in optoelectronic packages that have low power consumption and low packaging cost.
The interposer 106 has one or more optical conduits 108 built into the interposer 106. In an implementation, the optical conduits 108 may include a waveguide or a photonic wire. In a silicon photonics implementation, a ribbed and/or rectangular waveguide version of the optical conduits 108 may transmit or guide (“conduct”) infrared light as optical communications power.
The optical conduits 108 each generally include an inner core 110 surrounded by an outer cladding 112. The inner core 110 transmits optical power in one of several possible modes, while the outer cladding 112 confines the infrared light within the silicon inner core 110 due to differences in the refraction indices of silicon and silicon dioxide. In a rectangular waveguide implementation of the optical conduits 108, top and bottom claddings 112 of silicon dioxide on a silicon waveguide structure of rectangular cross-section confine the infrared light within the silicon. In a ribbed implementation of the silicon waveguide optical conduits 108, a rectangular rib on one side of the rectangular waveguide structure guides, directs, and/or bends the optical power wavefront. Example optical interfaces 114 optically join device optical conduits 116 & 118 of the optoelectronic computing chip 102 and of the optoelectronic memory stack 104 with the optical conduits 108 of the interposer 106, in this example.
In the example process for creating an optical interface 114, an inner core 110 of the optical conduits 116 & 108 may be made of a first material that conducts light at one or more wavelengths. The inner light-transmitting material may be silicon (Si), or other optical materials such as ZrO2, HfO2, TiO2, LiNbO3, Nb2O5, SrTiO3, or ZnS, for example. The outer cladding 112 of the optical conduits 116 & 108 has a lower refractive index than the material that makes up the inner core 110 of the optical conduits 116 & 108, so that the inner core 110 transmits the light and the outer cladding 112 reflects or refracts light that is leaving the inner core 110 back into the inner core 110. The outer cladding material may be silicon dioxide (SiO2) in the case of a silicon inner core 110, for example, or may be a polymer, such as polyimide, parylene, or other material with a suitable refractive index with respect to the material of the inner core 110 of the optical conduits 116 & 108.
In an implementation, through a direct bonding process, such as a direct oxide bonding process or an oxide-to-oxide direct bonding process, the outer cladding 112 is joined to a counterpart of the same material on the other side of the interface 114. In an implementation, the example direct oxide-bonding process takes place at room temperature, with minimal or no gaps, between surfaces being joined, and no detrimental extra layers created or introduced into the optical interface 114 during the process.
Depending on materials and process, there may be an allowable gap 200 or multiple partial gaps between the inner cores 110, at the surfaces being joined, or there may be no gaps. A permissible gap 200 has a gap size (vertical gap) less than one-quarter of the wavelength of the operational optical signal being conducted as electromagnetic waves. The gap 200 is shown as exaggerated in
The first direct oxide bond and the second direct bond join the first optical conduit 116 and the second optical conduit 108 together in a layerless join or a join with no detrimental intervening layers between the first optical conduit 116 and the second optical conduit 108. Likewise, the first direct oxide bond and the second direct bond join the first optical conduit 116 and the second optical conduit 108 together in a join with no gap or permissible gap between the first optical conduit 116 and the second optical conduit 108.
The optical interface 114 may also include electrical contacts associated with each of the first optical conduit 116 and the second optical conduit 108, wherein a first set of electrical contacts of the first optical conduit 116 are direct oxide bonded or direct bonded to a second set of electrical contacts of the second optical conduit at the optical interface 114.
In an implementation, an example apparatus includes a first optical conduit 116 on a first side of an optical interface 114 of a photonic device, a second optical conduit 108 on a second side of the optical interface 114 of the photonic device, and a first direct oxide bond between outer claddings 112 of the first optical conduit 116 and the second optical conduit 108. There is a second direct bond between inner cores 110 of the first optical conduit 116 and the second optical conduit 108. The apparatus may further include a first optical component 102 on the first side of the optical interface 114, the first optical component 102 having at least a first planar surface exposing a cross-section of the first optical conduit 116, and a second optical component 104 on the second side of the optical interface 114. The second optical component 104 also has at least a second planar surface exposing a cross-section of the second optical conduit 108, which may be an optical waveguide. The second optical conduit 108 also has an inner core 110 and an outer cladding 112 around the inner core 110.
The first direct oxide bond between the outer claddings 112 of the two optical conduits 116 & 108 can be an oxide bond formed at room temperature, such as a ZIBOND brand of direct oxide-to-oxide bonding (Xperi Corporation, San Jose, CA). The second direct bond of the inner cores 110 can be a metal-to-metal, semiconductor-to-semiconductor, or photonic-material-to-photonic-material bond formed at an annealing temperature used for strengthening, curing or setting the previous direct oxide bond for the outer claddings 112. For example, two surfaces of silicon may form crystal lattice bonds at the optical interface with each other. ZIBOND bonding is a low-temperature wafer-to-wafer or die-to-wafer bonding technique between wafers or dies with the same or different coefficients of thermal expansion (CTE), using a low-temperature homogeneous (oxide-to-oxide) direct bonding technology. ZIBOND bonding offers multiple benefits over conventional bonding techniques such as adhesives, anodic bonding, eutectic bonding and glass frit. Bonding is performed at room temperature, which enhances overall yield and reliability, by eliminating the negative effects associated with coefficient of expansion (CTE) mismatch, warpage and distortion. Higher throughput and lower cost-of-ownership are realized by using industry-standard wafer alignment and bonding equipment. Without requiring elevated temperature or high pressure during bonding, the high-throughput of the ZIBOND bonding fabrication process minimizes cost-of-manufacturing during mass-production for high volume market applications. During ZIBOND processing, industry standard dielectric surfaces like silicon dioxide or silicon carbide nitride are polished to low surface roughness using conventional chemical-mechanical polishing (CMP) tools, and nitrogen-based chemistries are applied through conventional plasma etch processing. Prepared wafer surfaces are then simply aligned and placed together, resulting in the spontaneous formation of chemical bonds between die and/or wafers. A very strong, low distortion chemical bond with a bond strength about half the strength of silicon can be obtained at room temperature, and a reliable hermetic bond stronger than silicon can be obtained after moderate heating to about 150° C. in batch processes outside of the alignment and placement tool, for example.
In one instance, the optical interface 114 may have a rectangular cross-section, a square cross-section, or a polygonal cross-section in a plane of the optical interface 114. In some cases, the first optical conduit 108 on one side of the optical interface 114 has a noncircular, rectangular, square, or polygonal cross-section and the other optical conduit 116 has a circular cross-section in the plane of the optical interface.
An example optoelectronic apparatus includes an optical trace 404 bonded to a die or a chip 406 made at least in part of a semiconductor material, and a direct oxide bond between the optical trace 404 and the die or chip 406. The direct oxide bond may be an oxide-to-oxide bond formed at room temperature or at a temperature near or below room temperature. Material used for the waveguides 400 employed at optical traces 404 are optically transparent or photonic materials, including some semiconductors. The direct oxide bond itself can be optically transparent, or optically transparent at least in part.
In one layout, the optical trace 404 transmits a light or electromagnetic radiation between a first die or chip 102 and a second die, chip 104, or stack of dies. The optical trace 404 may be directly oxide-bonded to a first die or chip 102 and to a second die or chip 104. The optical trace 404 can provide an optical path between the first die or chip 102 and the second die 104 or chip without conventional inline optical couplers.
In an implementation, on a given die or microchip 406, the optical trace 404 may be a rib member 408 of an optical waveguide. The rib member 408 is direct bonded 410 to a semiconductor material of the die or microchip 406 to make the optical waveguide 402 serving as an optical trace 404, wherein the optical waveguide 402 comprises the rib member 408, the direct bond 410, and the semiconductor material of the die or the microchip 406.
The low-temperature direct bonding techniques are used to attach the optical traces 404 to chips 502 & 504 & 506 and to other optoelectronic components with example optical interfaces 114 that eliminate the need for optical couplers in chip-to-chip communications. The example optical interfaces 114 provides direct bonding waveguide interface joints between the optical traces 404 and optoelectronic microchips 502 & 504 & 506.
To make the example apparatus or integrated optical waveguide 600, an example process includes coupling optical components and electrical contacts together across an optical interface at a single bonding surface between the wafers, while simultaneously fabricating photonic waveguides for optical routing in the optoelectronic package or structure being formed. The use of low-temperature direct oxide bonds in this example process allows unification or convergence of silicon photonics and microelectronics together in the same wafer-produced package. Some aspects of the example process can also be used to form waveguides in die-to-die processes or to perform vertical direct optical coupling and electrical coupling of contacts from one die to another with minimal or no gaps and no detrimental extra layers, and without requiring underfill or bumps.
In one implementation, a channel 602 is etched in a first wafer 604 of silicon to make a silicon pillar 606 surrounded by the channel 602 in the first wafer 604. The channel 602 may be filled with a dielectric that has a suitable refractive index relative to the silicon to create an optical conduit and part of a waveguide.
A recess 608 is formed in the first wafer 604 of silicon in an area around the channel 602 and silicon pillar 606. A first oxide material is deposited in the recess 608 for later purposes of direct oxide-bonding between wafers, at low-temperature.
On a second wafer 610 made of silicon, a trench 612 is etched, having an angled side 614, such as at least one 45 degree side in the trench 612. A second oxide is deposited in the trench 612. The oxide deposited in the trench 612 of the second wafer 610 may be the same oxide as deposited in the recess 608 of the first wafer 604.
The trench-side of the second wafer 610 is bonded to at least an oxide layer 616 of a third wafer 618 to make an interposer 620. The interposer 620 may be thinned at this point, as desired. The first wafer 604 is then bonded to the interposer 620 by direct oxide-to-oxide-bonding of the first oxide in the recess 608 of the first wafer 604 to at least the oxide in the trench 614 of the second wafer 610 to make the example integrated waveguide 600 of silicon, or other optical apparatuses bonded at a single waveguide interface plane with direct oxide bonding.
Prior to bonding the first wafer 604 to the interposer 620 to make the integrated waveguide 600, the silicon pillar 606 of the optical conduit of the first wafer 604 is aligned with the angled side 614 of the trench 612 of the interposer 620 in order to fabricate an optical pathway 622 that connects optical power between a component 624 mounted on the first wafer 604 and the integrated waveguide 600. In an implementation, the integrated waveguide 600 guides the optical power around a corner formed by the angled side 614 of the trench 612 of the interposer 620, that is, from a vertical silicon pillar 606, for example, to a horizontal layer 626 of the silicon.
In an implementation, aligning the silicon pillar 606 with a 45 degree side 614 of the trench 612 prior to the bonding makes an integrated waveguide 600 capable of guiding infrared light propagating vertically from the silicon pillar 606 through a 90 degree change in direction into the horizontally disposed silicon layer 626 in the interposer 620.
The example process may use direct oxide-to-oxide-bonding between the oxide in the recess 608 of the first wafer 604 and the oxide in the trench 612 of the second wafer 610 or interposer 620, with the bonding at room temperature, which favors microelectronics located in the same vicinity, as higher temperatures can be detrimental to the microelectronics. The low bonding temperature also allows optoelectronic components with III-V semiconductor compounds to be fully finished and mounted prior to the bonding. Conventionally, components with III-V semiconductor compounds need special handling because they cannot withstand conventional microelectronics bonding temperatures.
The silicon of the pillar 606 and the silicon in the top horizontal layer 626 of the interposer 620 are joined together at the same time as the oxide interface, with spontaneous crystal lattice bonding at an annealing temperature slightly higher than room temperature.
At block 802, a channel is etched in a first wafer of silicon to make a silicon pillar surrounded by the channel in the first wafer. The method is not limited to silicon, but can be implemented in silicon as an example, to combine optical communications with microelectronics in a silicon photonics package.
At block 804, the channel may be filled with a dielectric or other material of suitable refractive index. The dielectric and the pillar being surrounded by the dielectric comprise an optical conduit for infrared light, in the case of silicon.
At block 806, the silicon on one side of the first wafer is etched or otherwise removed to form a recess around the optical conduit on that side of the first wafer.
At block 808, a first oxide is deposited in the recess.
At block 810, a trench is etched on a second wafer made of silicon, the trench having an angled side, such as at least one 45 degree side.
At block 812, a second oxide is deposited in the trench of the second wafer. The second oxide may be the same oxide compound as deposited in the recess of the first wafer, at block 808, or may be a different oxide.
At block 814, a trench side of the second wafer is bonded to an oxide layer of a third silicon wafer, such as a silicon on insulator (SOI) wafer, to make an interposer.
At block 816, the first wafer with the optical conduit is bonded to the interposer after alignment to make an integrated waveguide of silicon, including direct oxide-to-oxide-bonding of the first oxide in the recess of the first wafer to at least the second oxide in the trench of the second wafer.
In the specification and following claims: the terms “connect,” “connection,” “connected,” “in connection with,” and “connecting,” are used to mean “in direct connection with” or “in connection with via one or more elements.” The terms “couple,” “coupling,” “coupled,” “coupled together,” and “coupled with,” are used to mean “directly coupled together” or “coupled together via one or more elements.”
While the present disclosure has been disclosed with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations possible given the description. It is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of the disclosure.
The patent application is a continuation of U.S. patent application Ser. No. 17/507,019 to Huang et al., filed Oct. 21, 2021, entitled, “Integrated optical waveguides, direct-bonded waveguide Interface joints, optical routing and Interconnects,” which claims the benefit of priority to U.S. patent application Ser. No. 16/247,262 to Huang et al., filed Jan. 14, 2019, now U.S. Pat. No. 11,169,326, issued Nov. 9, 2021, entitled, “Integrated optical waveguides, direct-bonded waveguide Interface joints, optical routing and Interconnects,” which claims the benefit of priority to U.S. Provisional Patent Application No. 62/635,314 to Huang et al., filed Feb. 26, 2018, entitled, “Integrated optical waveguides, direct-bonded waveguide Interface joints, optical routing and Interconnects,” the entire contents of each of which are hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62635314 | Feb 2018 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16247262 | Jan 2019 | US |
| Child | 17507019 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17507019 | Oct 2021 | US |
| Child | 18508556 | US |
