INTEGRATED PLATFORMS FOR MICROSCALE SPATIALLY-RESOLVED ELECTROCHEMICAL MEASUREMENTS

Abstract

A complementary metal-oxide-semiconductor sensor array includes an active sensing area of pixels arranged in an array with a pitch, each pixel including an exposed surface electrode alongside switches and logic gates, and non-overlapping clocks configured to rapidly charge and discharge the exposed surface electrode, wherein control signals steer a switched output current between shared column outputs.

Description

BACKGROUND OF THE INVENTION

Capacitive sensing and electrochemical impedance spectroscopy (EIS) are appealing technologies for miniaturized and integrated biochemical and cellular measurement systems because of their low cost and simple instrumentation. Yet despite their appeal, EIS biosensors can suffer from low dynamic range and low chemical specificity.

Moreover, amid the continued adoption of integrated circuit technology in biomedical applications, the ion-sensitive field effect transistor (ISFET) has cemented an important commercial role. CMOS compatible ISFET platforms can scale up to large dense arrays, enabling high throughput DNA sequencing and assays, cellular metabolism sensing, chemical imaging, and food safety screening. However, longer-duration applications such as cell culture monitoring can be challenging for ISFETs due to drift and flicker noise.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the innovation in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

In general, in one aspect, the invention features a complementary metal-oxide-semiconductor sensor array including an active sensing area of pixels arranged in an array with a pitch, each pixel including an exposed surface electrode alongside switches and logic gates, and non-overlapping clocks configured to rapidly charge and discharge the exposed surface electrode, wherein control signals steer a switched output current between shared column outputs.

In another aspect, the invention features an ion-sensitive field-effect transistor (ISFET) circuit including an array of ion-sensitive field-effect transistor pixels, each pixel comprising a first PMOS transistor and a second PMOS transistor, the first PMOS transistor acting as a sensing ISFET and the second PMOS transistor acting as a reference MOSFET, and a readout circuit.

In another aspect, the invention features a complementary metal-oxide-semiconductor sensor array including an active sensing area including pixels arranged in an array, each pixel including an exposed surface electrode, a high-frequency impedance circuit, an nMOS ISFET configured for pH sensing, and a photodetector.

In another aspect, the invention features a system including a 100×100 CMOS EIS sensor array that uses an area-efficient two-phase switching scheme to measure the mutual capacitance between pairs of nearby pixels.

In another aspect, the invention features a system including a high-density CMOS microelectrode array that can manipulate fringe fields of a measured pixel by configuring clock phases and bias voltages within a moving kernel of neighboring pixels.

These and other features and advantages will be apparent from a reading of the following detailed description and a review of the associated drawings. It is to be understood that both the foregoing general description and the following detailed description are explanatory only and are not restrictive of aspects as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the present invention will become better understood with reference to the following description, appended claims, and accompanying drawings where:

FIGS. 1a, 1b and 1c illustrate a high frequency imaging array.

FIG. 2 illustrates a CMOS sensor array.

FIGS. 3a, 3b, 3c and 3d illustrate code division multiplexing.

FIG. 4 illustrates operation of an in-pixel ISFET chopping circuit.

FIG. 5 illustrates an ISFET array.

FIG. 6 illustrates readout signal paths.

FIG. 7 illustrates a circuit diagram of a biosensor array.

FIGS. 8a, 8b and 8c illustrate addressing logic

FIGS. 9a, 9b, 9c and 9d illustrate a chip.

FIGS. 10A, 10 b, 10c illustrate a two-phase mutual capacitance measurement.

FIGS. 11A, 11 b illustrate mutual capacitance imaging.

FIG. 12 illustrates an exemplary pixel and array schematic.

FIG. 13a illustrates a simple capacitance model.

FIG. 13b illustrates two sets of overlapping clocks.

FIG. 14 illustrates a pixel schematic and overall architecture.

FIG. 15 illustrates tables.

FIG. 16 illustrates an array.

FIG. 17 illustrates EIS imaging.

FIG. 18 illustrates algae.

FIG. 19 illustrates algae.

FIG. 20 illustrates algae.

FIG. 21 illustrates single cells.

FIG. 22 illustrates mixed algae.

FIG. 23 illustrates classifying algae.

DETAILED DESCRIPTION

The subject innovation is now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It may be evident, however, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the present invention.

Radio frequency dielectric spectroscopy is an attractive paradigm for low-cost non-optical imaging of cells and bioparticles. While traditional electrochemical impedance spectroscopy is often performed at lower frequencies, working at radio frequencies can overcome ion screening effects and detect features farther from electrode surfaces. In a first embodiment, the present invention is a 64×64 sensing array with 10 μm pixels in 180-nm CMOS, supporting switching frequencies up to 100 MHz. The array features code-division multiplexed readout of all 64 rows simultaneously, which offers opportunities for extended integration times, higher frame rates, improved common-mode rejection, and new wide-bandwidth sensing modalities.

Capacitive sensing and electrochemical impedance spectroscopy (EIS) are appealing technologies for miniaturized and integrated biochemical and cellular measurement systems because of their low cost and simple instrumentation. Yet despite their appeal, EIS biosensors can suffer from low dynamic range and low chemical specificity. One cause of this trend is Debye screening, which causes kHz-range AC measurements at physiological conditions to be sensitive to chemical conditions and analytes within only a few nanometers of the working electrode. Exceptions to this rule are when arrays of electrodes can be placed far apart and used in coordination, such as in electrical impedance tomography.

To overcome ion screening, advances have been made in high frequency (1 MHz) impedance spectroscopy, which can enable measurements of features farther from the surface. However, high frequency dielectric spectroscopy remains under-explored, in part due to the challenge of designing microelectronics with suitably low noise, high bandwidth, high density, and low parasitics.

The present invention is a novel dielectric sensing array capable of producing electrochemical images at switching frequencies up to 100 MHz. In addition to traditional row-scanned image acquisition, the new sensor array can acquire data using code division multiplexing (CDM), which records all rows at once using orthogonal spreading codes. CDM can offer opportunities for extended integration times, faster frame rates, and improved rejection of parasitic capacitances within the array.

CMOS Sensor Array Design: Pixel Design

The active sensing area has 4,096 pixels arranged in a 64×64 array with a 10 micron pitch. As shown in FIGS. 1a, 1b and 1c, each pixel contains an exposed surface electrode alongside four switches and two logic gates. Non-overlapping clocks Φ₁ and Φ₂ rapidly charge and discharge the electrode, and control signals θ₁ and θ₂ steer the switched output current between two shared column outputs. In this prototype, the clocks are generated off-chip.

More specifically, in FIG. 1a, each sensing pixel electrode is charged and discharged with high frequency non-overlapping clocks Φ₁ and Φ₂, and the output signal current is steered into one of two output columns by a slower control signal θ. In FIG. 2b, the array is designed to form an electrochemical image of cells and particles on the surface, based on the effective capacitance at each pixel. In FIG. 1c, by changing the behavior of θ, the array supports both traditional time-division readout, as well as a code-division mode in which all rows can be read out simultaneously.

CMOS Sensor Array Design: Column Amplifiers

In FIG. 2, an exemplary CMOS sensor architecture 200 is shown. Column outputs from the array are directed into a high-bandwidth differential current buffer, followed by a pair of integration capacitors, and a pair of output buffers. The differential output voltage is then digitized by a 16-bit PCI data acquisition card, typically at 100 kS/s. On this exemplary chip, the 64 columns are multiplexed onto 8 independent readout channels.

The current buffers are gain-boosted cascode amplifiers with a simulated bandwidth of 400 MHz. An integration capacitor creates a low-pass filter with a time constant of 20 μs, averaging out the switched pixel currents. The simulated low frequency transimpedance gain is 110 dBΩ, and the simulated input referred noise floor of the system is 1 fF_rms, assuming a 1 kHz integration bandwidth, f_clk=50 MHz, and (V_TIA−V_bias)=200 mV.

CMOS Sensor Array Design: Code Division Readout

Code Division Multiplexing (CDM) is a widely used technique in telecommunications. By assigning a unique orthogonal spreading code to each user, CDM enables multiple users to access one channel simultaneously. This concept can also be applied to sensor arrays, enabling concurrent readout of signals from multiple pixels, and overlapping pixel integration times for improved sensitivity. Our proposed sensor array supports both time division and code division.

Our CDM is shown in FIGS. 3a, 3b, 3c an 3d. Here, each row is assigned a 64-bit code, represented by one row of the binary matrix shown in FIG. 3a. These codes are simple to generate with a few shift registers and multiplexers (FIG. 3b), and have the useful feature of constant code weight, which helps to reduce distortion caused by changes to the common-mode output level over time. To generate the codes, we start with an orthogonal 4×4 matrix having a constant row sum of −2, expand it a 16×16 matrix (M₁₆) and then to 64×64 (M₆₄, shown in FIG. 3a):

$\begin{array}{cc}{M}_1=\left[\begin{array}{cccc}+1& -1& -1& -1\\ -1& +1& -1& -1\\ -1& -1& +1& -1\\ -1& -1& -1& +1\end{array}\right]& \left(\left(1\right)\right)\\ M_{26}=\left[\begin{array}{cccc}+M_4& -M_4& -M_4& -M_4\\ -M_4& +M_4& -M_4& -M_4\\ -M_4& -M_4& +M_4& -M_4\\ -M_4& -M_4& -M_4& +M_4\end{array}\right]& \left(2\right)\\ M_{61}=\left[\begin{array}{cccc}+M_{16}& -M_{16}& -M_{16}& -M_{16}\\ -M_{16}& +M_{16}& -M_{16}& -M_{16}\\ -M_{16}& -M_{16}& +M_{16}& -M_{16}\\ -M_{16}& -M_{16}& -M_{16}& +M_{16}\end{array}\right]& \left(3\right)\end{array}$

The spreading code for each row is used to control θ (FIG. 1a), modulating the polarity of the differential output current. In our measurements, we typically use a code chip rate of 1 kHz. Later, after the signals are digitized, each column time series is multiplied by M₆₄ to retrieve the data from each row. Compared to conventional time division, code division can be leveraged for either longer integration times or faster frame rates (FIG. 1c). Another feature of CDM is that it can shield sensing pixels from common-mode interference from parasitic capacitances to nearby electrodes. As neighboring rows now carry their own orthogonal codes and are active concurrently, the net charge injected through parasitic capacitances is reduced (FIGS. 3c and 3d).

Ion sensitive field effect transistors (ISFETs) are CMOS-compatible pH sensors which have been adopted for a wide range of biochemical sensing applications. Drift and low-frequency noise are perennial challenges for these small charge-sensitive devices. However, ISFET designers have often avoided the common circuit solution of chopper stabilization due to understandable concern that the switching will disturb the sensing gate. In a second embodiment, we provide a new configuration which modulates the source and drain voltages of the ISFET, reducing 1/f noise and drift with negligible disturbance of the sensing gate. Using in-pixel chopping, the circuit achieves a three-fold reduction in drift along with suppression of 1/f noise.

Amid the continued adoption of integrated circuit technology in biomedical applications, the ion-sensitive field effect transistor (ISFET) has cemented an important commercial role. CMOS-compatible ISFET platforms can scale up to large dense arrays, enabling high throughput DNA sequencing and assays, cellular metabolism sensing, chemical imaging, and food safety screening.

However, longer-duration applications such as cell culture monitoring can be challenging for ISFETs due to drift and flicker noise. ISFET drift is thought to originate from trap effects and transport at the sensing electrode interface, and it is affected by temperature, pH, and ion migration. Flicker (1/f) noise comes from more familiar electronic sources, and it increasingly affects ISFET transistors as their geometry scales down to support dense arrays.

It is possible to dynamically adjust the ISFET bias to reduce drift, although this requires significant supporting circuitry and may be challenging to use within arrays. Correlated double sampling (CDS) is also possible, but CDS filters out signals below the switching frequency, which is unfortunate for long-term pH monitoring. Another possibility is a differential measurement between an ISFET and a reference ISFET (REFET), but this method only suppresses the common-mode drift between the two devices. Finally, it is possible to periodically cycle the solution potential, and in turn V_gs, resetting the surface charge each time and producing a repeatable drift pattern. While effective, this method does not address 1/f noise, and large low-frequency switching transients could affect nearby cells and electrodes.

This embodiment of the present invention is an in-pixel chopping method to simultaneously reduce the drift and 1/f noise of a CMOS-integrated titanium nitride (TiN) ISFET. It has long been understood that MOSFET 1/f noise can be reduced by cycling between accumulation and inversion. However, directly chopping the solution potential at high frequencies is impractical. We have a new balanced ISFET switching scheme to modulate the source and drain voltages instead of the chemical gate. In addition to lowering 1/f noise, cycling V_gs helps to reduce the mean electric field at the electrode, supporting slower ion crossing rates and reducing drift.

In-Pixel Chopping Circuit

To chop the ISFET bias with minimal disturbance of the sensing gate, we designed a balanced PMOS switching structure 400, illustrated in FIG. 4. During the standby phase (Φ=0), the ISFET's source and drain are both tied to V_M, and the device is off. V_G is set indirectly, through V_REF. During the operating phase (Φ=1), the PMOS source is raised to V_H such that the ISFET enters strong inversion. The drain is voltage-clamped at V_TIA while the current is measured by a transimpedance amplifier. We tested the chopping rate between 100 Hz and 10 kHz, but it can also support higher frequencies.

Much of the switching noise injected onto the gate through C_gs and C_gd can be compensated by simply setting V_M near the midpoint between V_H and V_TIA. Additionally, since the chemical interface capacitance is much larger than the device capacitances of the CMOS transistors, capacitive voltage division will further attenuate the residual switching noise. (With 100 μm2 gate area, the chemical double-layer capacitance is approximately 14 pF.)

Reductions in 1/f noise and drift can both be achieved with the proposed scheme. First, it is clear that the chopping should cycle the device between strong inversion and accumulation, which refreshes charge traps in the MOSFET channel to destroy the memory that generates 1/f noise. Although it is more typical to modulate the gate voltage, since the ISFET's chemical interface capacitance is much larger than the device capacitances, modulating the source terminal achieves the same effect while being gentler on the reference electrode and surface charges. Second, although the precise causes of drift in ISFETs are complex, several studies have focused on possible electrochemical causes. It seems reasonable to theorize that mechanisms such as ion migration will be affected by the mean vertical electric field experienced at the sensing surface. Since toggling the ISFET V_gs reduces the effective DC field seen by the surface charges, we anticipate that the proposed switching structure may also reduce ISFET drift.

In FIG. 5, an exemplary ISFET circuit 500 is shown.

ISFET Pixel and Array Design

As shown in FIG. 5, each pixel hosts two PMOS transistors, with one acting as the sensing ISFET and the other one available as a reference MOSFET. Both devices have W=440 nm and L=300 nm. The voltage references are set to V_H=3.3V, V_M=2V, and V_TIA=1.2V. V_ref is typically held near 2V, and it can be fine-tuned depending on the V_TH and chemical potential offsets. All switches are minimum size transmission gates to reduce clock feedthrough and charge injection.

The array has 36 pixels and the top metal gate area for each ISFET is 100 μm2. Half of the ISFETS are designed with standard silicon nitride (Si₃N₄) passivation above the sensing gate. The other half are fabricated with the passivation layer removed and the top metal (aluminum) exposed. We post-process the chip to etch the aluminum, exposing its vias and titanium nitride (TiN) diffusion barrier layer. Although ISFET gates are more commonly made from dielectrics (Si₃N₄, Al₂O₃, or Ta₂O₅), TiN is a highly stable ceramic material commonly used in semiconductor foundries, and a conductive ISFET gate may additionally lend resistance to charge screening from some absorbates.

Readout Circuits

In FIG. 6, an exemplary readout circuit 600 is shown. The readout circuit 600 includes a voltage-clamped current buffer, a programmable-gain transimpedance stage, and a voltage buffer. After a 2nd order anti-aliasing filter, the output voltage is digitized by a 16-bit PCI data acquisition card at sample rates up to 100 kS/s.

The voltage-clamped current buffer consists of a common-gate amplifier with gain boosting, which lowers the input impedance and clamps its input voltage to V_TIA. To reduce 1/f noise, large transistors are used, and the NMOS current mirror from is replaced with a resistor. This current buffer is designed to operate with V_TIA ranging from 0.8V to 1.4V while maintaining its input impedance below 100Ω.

Following the current buffer is a PMOS common source amplifier with on-chip programmable load resistance and a PMOS source follower as the output stage. The gain of the readout path is −0.8 V/V, and the PMOS ISFET contributes >90% of the total input referred noise below 1 kHz.

In a third embodiment, the present invention is a large-scale fully integrated multimodal sensor array for biological imaging. The 512×256 sensor array can perform spatially resolved electrochemical impedance spectroscopy (EIS) with switching frequencies up to 100 MHz, acquire multicolor optical images, and sense pH using titanium nitride (TiN) ion sensitive field effect transistors (ISFETs). The chip features code-division multiplexed (CDM) readout of groups of pixels simultaneously, enabling extended integration times at a given frame rate. The system may be implemented in 180-nm CMOS with 9.5 μm×11.5 μm pixels. Its overall fill factor is 57%, including peripheral control and readout circuits, yielding a wide-field spatially resolved multimodal biosensing platform for advanced cell culture applications.

Integrated circuits continue to gain traction neural in a diverse array of biomedical applications, including neural recording systems, DNA sequencing instruments, and smart cell culture platforms which demand creative solutions for dense multimodal sensor integration.

There are several types of CMOS-compatible sensors that can provide useful measurements of growing cell cultures. The most classical options are photodiode arrays, which can be used for optical imaging of cells' shapes and positions even without lenses, although lens-free contact imaging often does not reach the diffraction limit. Cellular metabolism can be monitored indirectly through pH changes, recorded by ion-sensitive field-effect transistors (ISFETs). Electrochemical impedance spectroscopy (EIS) can provide spatially resolved images of the local conductivity and dielectric constant, which relate to properties of cell membranes, proteins, and extracellular matrix. EIS measurements are also frequency-dependent, offering another dimension of information. Recognizing the diversity and multiscale nature of cellular processes, a multimodal lens-free CMOS sensor array with a sufficiently large active sensing area could enable wide-field monitoring of cells, colonies, or even whole tissues at a fraction of the size and cost of traditional microscopes.

The present invention is directed towards a multimodal CMOS sensor array that measures radio-frequency impedance spectra, pH, and visible light, across 131,072 pixels. Intended for long-term cell culture monitoring, this design prioritizes a large uninterrupted sensing area. It achieves a 57% fill factor, with the active sensing region occupying more than half of the chip surface. With thousands of co-located EIS, pH, and optical measurements, this system can capture detailed spatially resolved recordings of cellular growth and metabolism.

CMOS Sensor Array Design: Pixel Design

In FIG. 7, an exemplary circuit diagram 700 of a biosensor array is shown. The active sensing area has 131,072 pixels arranged in a 512×256 array. Each pixel contains an exposed surface electrode, a high-frequency impedance measurement circuit, an nMOS ISFET for pH sensing, and three photodiodes for color-sensitive optical imaging. The current is steered between two shared column outputs using another set of control signals (θ and θ⁻). Depending on how θ is configured, the readout can support either time-division multiplexing (TDM) or code-division multiplexing (CDM). Only one type of sensor is active at a time for minimal crosstalk between sensing modes, and inactive pixels can optionally be routed to a dummy column to reduce pixel-to-pixel parasitic coupling.

1) EIS Measurement: The EIS circuits support impedance measurements up to 100 MHz using a switched capacitor circuit with nonoverlapping clocks (Φ₁ and Φ₂) to rapidly charge and discharge the electrode. In comparison to traditional kilohertz EIS, radio frequency operation reduces Debye screening, producing measurements sensitive to the dielectric environment farther from the electrode surface.

2) Color-Sensitive Optical Imaging: To support ratiometric absorption measurements of cell optical density across multiple wavelengths, each pixel contains a photodetector in which three diodes share the same P-substrate, but have isolated N-well cathode contacts which are biased to V₀, V₁, and V₂. The photodiodes are surrounded by guard rings for improved isolation. FIG. 9a illustrates a chip fabricated in 180-nm CMOS, and wirebonded to a small chip-on-board module. FIG. 9b illustrates a cross-section of a pixel. FIG. 9c illustrates a 3.9×6.4 mm² die. FIG. 9d illustrates that each multimodal pixel occupies 11.5×9.5 μm². Depending on the bias voltages, the electric field distribution will cause the cathodes to collect photons absorbed at different depths in the P-substrate. By separately collecting currents from each cathode contact, the sensor can achieve tunable wavelength selectivity.

Although there is a sensitivity penalty, this arrangement allows is to assemble a color image from multiple exposures, without a color filter mosaic. The photodiodes have a minimal impact on the total sensor area because they are positioned underneath the required spacing between the top metal electrodes.

3) pH Sensing: An ISFET is a transistor whose floating gate is connected to an electrode exposed to an ionic solution, and which measures pH through the relationship between the gate's surface charge and the device's threshold voltage. The pH measurement is performed with both EIS switches disabled, but these switches can optionally also be used to reset trapped charges and reduce ISFET drift.

Demonstrations of ISFETs in standard CMOS often use Si₃N₄ as the gate passivation layer or deposit additional pH sensitive dielectric materials. Here, instead of depositing additional layers, we use a single post-processing step to chemically etch away the aluminum top metal, exposing the electrodes' underlying titanium nitride (TiN) diffusion barrier, which is a conductive and highly stable material that can be used for both pH and impedance sensing.

CMOS Sensor Array Design: Column Amplifiers

Column outputs from the array are directed into a high-bandwidth differential current buffer (FIG. 7). The output voltage is low-pass filtered, amplified, and then digitized by an external 18-bit ADC at 500 kS/s. The current buffers are gain-boosted common gate amplifiers with a simulated bandwidth of 200 MHz and are used to maintain a low input impedance as well as to clamp the input voltage. Differential chopping is used to suppress 1/f noise and offsets.

All of the columns are multiplexed onto a single readout channel, which simplifies calibration and reduces the chip area and design complexity at the cost of lower frame rates. This tradeoff is acceptable since recording cell culture growth typically involves time-lapse imaging over the course of hours or days.

CMOS Sensor Array Design: Code Division Readout

The addressing logic supports either TDM or CDM readout (FIGS. 8a, 8b 8c), where FIG. 8a illustrates a timing diagram comparison between time-division and 256-bit code-division readout, and FIG. 8b illustrates a binary matrix of 256-bit orthogonal codes. In TDM, pixels are measured one at a time. In contrast, CDM enables concurrent readout from blocks of pixels to extend the integration times for a given frame rate and improve the common-mode shielding from neighboring pixels.

We implemented an EIS array with 64-bit CDM readout in the past, and here we further expand the hardware capabilities to support up to 256-bit codes. A set of orthogonal codes is generated by on-chip logic [FIG. 8c], and each code is assigned to a row. The modulated currents from each row are summed into the same column, and after the signals are digitized, the time series of each column is multiplied by the encoding matrix to decode the data for each row.

All codes have a constant sum of (√(code length)), which helps to reduce distortion, but which adds a dc offset to the output current that can saturate the column amplifier. In consideration of each sensor's different typical current range, we often use 256-bit CDM for optical imaging, 64-bit CDM for EIS, and TDM for pH sensing.

With a 3 kHz code clock, EIS and optical images are each acquired in ≈50 s. For pH sensing, we allocate 1 ms/address, or ≈2.5 min per full frame. During time-lapse cell culture recordings, the system can record a set of full-frame EIS, pH, and optical images every 5 min.

In another embodiment, the present invention is directed towards a an integrated sensor array for microscale electrochemical impedance spectroscopy (EIS) imaging. In one implementation, the system is implemented in 180 nm CMOS with 10 μm×10 μm pixels. Rather than treating each electrode independently, the sensor is designed to measure the mutual capacitance between programmable sets of pixels. Multiple spatially-resolved measurements can then be computationally combined to produce super-resolution impedance images.

As articulated above, electrochemical impedance spectroscopy (EIS) is a powerful tool for chemical and biological sensing, with numerous applications in cell culture monitoring and biomolecular diagnostics. However, while biological samples have important spatial variation in their conductivity and dielectric properties, impedance is often recorded at only a single point in space. Some approaches add spatial dimensions using scanning probes or small arrays of macroscale electrodes, but many opportunities remain to take advantage of the density and scale of CMOS integrated electrode arrays. Integrated impedance imaging arrays can offer greater throughput than discrete electronics, faster acquisition than scanning probes, and finer spatial resolution than existing impedance tomography systems.

To address these challenges, we designed a 100×100 CMOS EIS sensor array that uses an area efficient two-phase switching scheme to measure the mutual capacitance between pairs of nearby pixels. The pixel grid pitch is 10 microns, and a measurement from the array can be considered as a radio-frequency impedance image which is a function of both the sensor parameters and the spatial distribution of dielectric properties within the sample above the sensor. The pixels are addressable in a pairwise manner. For example, we can record an image that represents the impedance between each electrode and the pixel one position to its left; we can then acquire a second image that describes the mutual capacitance between each pixel and the electrode two positions to its left.

By acquiring impedance images with different pairwise pixel offsets, we can assemble a high-resolution composite image from multiple frames of the same scene, using oversampling principles similar to those used for super-resolution optical image reconstruction. Compared to previous CMOS capacitance imaging arrays, the present invention's scheme only requires one extra pair of switches per pixel.

An exemplary two-phase sensing scheme of the present invention is shown in FIGS. 10a, 10b and 10c. FIG. 10a presents a model of two electrodes that are capacitively coupled to a buffer solution. C1 describes the capacitance that is only seen by electrode #1, and C2 is the capacitance that is only seen by electrode #2. CM is the mutual capacitance between these two electrodes, which may include distributed electric fields extending into the sample as well as parasitic capacitance within the sensor chip. We neglect the effects of Debye shielding because the circuit is operating at radio frequencies. We also assume that the capacitors charge faster than the switching cycle so that we can neglect any distributed resistance.

The electrodes are contained within pixels which can switch their bias voltages between multiple sources. The signal current I_SENSE from electrode #1 is routed to a column amplifier where it is integrated and measured. V_BIAS and V_STIMU are provided from external voltage references, and V_CM is the virtual ground potential of the current integrator. The timing diagram of the two sets of non-overlapping clocks is shown in FIG. 10b, where θ₁ and θ₂ are 180° out of phase.

Interestingly, if we set V_BIAS=V_CM, this circuit can be equivalent to a classical non-inverting switched capacitor integrator as shown in FIG. 10c. When both θ_1,2 and θ_2,1 are high, the voltage across C_M is V_STIMU−V_CM. When both θ_1,1 and θ_2,2 are high, C_M is discharged to 0V. Thus the average measured current can be expressed as I_SENSE=C_M (V_STIMU−V_CM)f_clk. Since the voltage across C₁ does not change, I_SENSE is only a function of C_M.

FIGS. 11a, 11b illustrate a process of scanning the sensor array to form one impedance image, and then varying the scanned pattern to create multiple different impedance perspectives. In this simplified example, we use a 3×3 kernel, where the indices of Pixel #1 and Pixel #2 from FIG. 10a are related by (i₂, j₂)=(i₁+δ_i, j_i+δj), where δ_i=δ_j=1. This kernel is scanned over the entire array to generate an image. The acquisition is repeated for different offset vectors (δ_i, δ_j), producing a collection of images with slightly different dependence on the sample's spatially varying impedance. To acquire all pairwise N×N kernels requires N²−1 images.

CMOS Sensor Array Design: Pixel and Array

Simplified schematics are shown in FIG. 12. The active sensing area has 10,000 pixels arranged in a 100×100 array. Each pixel can be driven by one of two pairs of non-overlapping input clocks (θ_1,1/2 and θ_2,1/2), whose relative phases are synthesized by an external delay lock loop. A set of control signals drive each row (R_A/B) and column (C_A/B), to determine the clock selection in each pixel. All switches are implemented as single NMOS transistors. After each pixel measurement, the NMOS switch gates are fully discharged to prevent stored charge from interfering with the next pixel scan. The output current of each pixel can either be routed to the readout circuit or to the V_STIMU voltage reference as shown in FIGS. 10a, 10b, 10c.

CMOS Sensor Array Design: Readout Circuit

The readout circuit shown in FIG. 12 includes chopping switches and a pair of integrators for signal amplification, followed by buffers that drive an external 500 kS/s 18-bit ADC. Differential chopping and correlated double-sampling are used to suppress the 1/f noise and offsets.

In still another embodiment, the present invention is a fringe field shaping CMOS capacitance imaging array.

As discussed herein, capacitive sensing and electrochemical impedance spectroscopy (EIS) serve a wide range of applications, from monitoring cell cultures to measuring neuron connectivity and activity, from industrial flow sensing to landmine detection. While many classical techniques measure the impedance at the surface of one working electrode at a time, more complex measurements take advantage of networks of multiple electrodes. Impedance tomography systems, for example, often interrogate pairs of elements within a small but strategically positioned electrode array. As larger and denser microelectrode arrays become available, more complex multi-electrode stimulation and measurement can enable new sensing modalities for impedance imaging with enhanced sensitivity and improved spatial resolution.

A system of the present invention includes a high-density CMOS microelectrode array, which can manipulate the fringe fields of the measured pixel by configuring the clock phases and bias voltages within a moving kernel of neighboring pixels. The circuit operates at radio frequency which extends the reach of the electric field and creates opportunities to leverage complex micron-scale interactions between the electric fields of groups of nearby pixels. This arrangement bears some relationship to both computational image sensors and impedance tomography, and it can be configured to perform some in situ signal processing while also reshaping the local electric field to extract additional information about a sample.

Fringe Field Shaping Model

FIG. 13a illustrates two pixels with a simple capacitance model. FIG. 13b illustrates two sets of non-overlapping clocks with 90° phase shift.

More specifically, a simplified model to analyze the fringe field shaping is shown in FIG. 13a, where two pixels are capacitively coupled to a buffer solution. The bulk solution is biased with V_REF, but most of the electric fields occur within tens of microns of the sensor surface. There is significant coupling between adjacent pixels (C_M). The chip operates at MHz frequencies, where one can largely neglect Debye screening. But at these frequencies, the fields are still pseudo-static and we exclude resistive elements for simplicity.

As shown in FIG. 13a, during the input, both pixels connect to V_BIAS for one clock phase, and then to either V_CM or V_STDBY. The pixels are controlled by two pairs of non-overlapping switching clocks (θ₁ and θ₂) with a common frequency but independent phases. Only the charge transferred through Pixel #1 is integrated by the readout circuit. If the phases of the two pixels' clocks are the same and V_STDBY=V_CM, then Pixel #2 serves to shield C_M, which can have sensing benefits as previously demonstrated. Under these conditions, the signal current is I_SENSE=C₁ (V_BIAS−V_CM)f_clk, where f_clk is the switching frequency. However, if there is a phase offset between neighboring pixels, more possibilities and complexities emerge. For example, FIG. 13b illustrates a 90° offset between two pixels. In this scenario, the integrated current is a function of C_M, expressed as I_SENSE=[C₁ (V_BIAS−V_CM)−C_M (V_BIAS−V_STDBY)]f_clk.

This two-pixel model can be generalized to a group of pixels driven by non-overlapping switching clocks with different phase offsets and biased by different output voltages. The prototype presented in this paper uses 5×5 pixel blocks to implement radial, vertical and horizontal kernels. The center pixel output is routed to the readout circuit and biased to V_CM, and the rest of the pixels are routed to V_STDBY. Physical models of these coupling capacitances will depend on the sensor parameters as well as the sample composition, and our goal is to use this complex parameter space to extract more information from spatially resolved EIS measurements.

In FIG. 14, a pixel schematic and overall architecture are illustrated. The active sensing area has 10,000 pixels in a 100×100 grid. Each pixel can use one of three sets of non-overlapping input clocks (θ_x− Φ₁ and θ_x− Φ₂), which are synthesized externally. To achieve both efficient pixel area usage and flexible kernel configurations, we use a set of pre-decoded control signals to drive each row (R_x) and column (C_x), to dictate the clock selection in each pixel. All switches are NMOS pass-gates. We also add a per-column (C_EN) control signals to disable pixels outside of the kernel. Bias voltages are supplied externally. Each pixel output can either be routed to the readout circuit or V_STDBY based on the two-dimensional row/column control. Each pixel contains an exposed electrode shared between the EIS measurement and a pH measurement with an ion-sensitive field effect transistor (ISFET). Here we focus only on the EIS operation. To reduce 1/f noise, the output current is chopped between two integrators, and buffered for an external differential-input 500 kS/s 18-bit ADC.

While many different configurations are possible, here we demonstrate three 5×5 configurations implementing radial, horizontal and vertical kernels. The detailed control signals for each configuration are shown in FIG. 15. Often, we elect to route the center pixel to ISEN SE, while the surrounding pixels are routed to V_STDBY. On-chip logic shifts the 5×5 pattern through the 100×100 array to capture one frame, producing an image of 96×96 complete kernels.

In yet another embodiment, the present invention is directed towards a CMOS electrochemical imaging array for the detection and classification of microorganisms.

Microorganisms account for most of the biodiversity on earth. Yet while there are increasingly powerful tools for studying microbial genetic diversity, there are fewer tools for studying microorganisms in their natural environments. The present invention provides CMOS electrochemical imaging arrays for detecting and classifying microorganisms. These microscale sensing platforms can provide non-optical measurements of cell geometries, behaviors, and metabolic markers. Integrated electrochemical imaging can contribute to improved medical diagnostics and environmental monitoring, as well as discoveries of new microbial populations.

Microorganisms include all living things with microscopic dimensions. A majority of microorganisms are unicellular, and this broad category includes species from all branches of life, including archaea, protists, bacteria, and fungi. Single cells may range in diameter from 0.1 μm to 100 μm, although unicellular organisms are often found in communities and their morphologies are highly dependent on their environment. In terms of sheer numbers of unique species, microbes represent the majority of the diversity of life on earth, and billions of species of microorganisms may remain undiscovered.

Developing integrated sensors for tracking diverse microorganisms could be especially useful for distributed environmental monitoring, where sensing living organisms can provide important information which is complementary to metagenomic studies. The diversity and abundance of microorganisms in field collected samples can serve as useful metrics for assessing the ecological health of soils, rivers, and oceans. These types of studies are increasingly important in monitoring the effects of global warming on ecosystems.

It is possible to image samples without lenses, especially when the distance between the object and the photodiode array becomes very small. Many modern image sensors have pixel sizes of only 1-2 μm. In addition to resolving objects larger than single pixels, lens-free imaging can support computational imaging modes when combined with structured illumination. However, there are limits to what can be measured optically, and other sensing modalities may offer complementary forms of information.

When a sample can be placed in direct contact with a sensor, it becomes possible to consider interrogating it electrochemically instead of optically. Electrochemical sensor arrays can be miniaturized and integrated, offering both challenges and opportunities. By their nature, microscale electrochemical measurements are often noisy and prone to drift and fouling, but they can also be quite fast and low cost. In some applications, non-optical imaging could avoid complications with dyes and photobleaching, and monitor organisms independent of lighting conditions.

pH Imaging

One type of chemical sensing which is readily achieved with semiconductor technology is pH sensing using ion sensitive field effect transistors (ISFETs). An ISFET is a transistor whose floating gate is sensitive to the surface potential of an exposed electrode. By selecting an electrode material with pH-sensitive surface charge groups, the transistor's inversion charge can be made a function of the pH. ISFETs can be constructed using many common oxides and nitrides, including SiO₂, SiN, Al₂O₃, HfO₂, and Ta₂O₅.

Integrated ISFET arrays have been designed at very large scales, especially for highly parallel DNA sequencing. ISFET arrays could also be interesting for monitoring microorganisms, as pH can serve as a proxy for pCO2 and other measures of metabolism. When combined with an ion-selective membrane, an ISFET may also be designed to detect other ions, such as potassium or calcium.

Reduction-Oxidation Imaging

In addition to sensing bulk chemical properties such as pH, other electrochemically active species can also provide information about a microorganism. Some researchers have developed systems which can produce electrochemical images of electroactive metabolites as they are released by tissue samples or bacterial biofilms. Cells on microelectrode arrays can also measurably affect the transport of bulk redox species to electrodes.

Impedance and Capacitive Imaging

Electrochemical impedance spectroscopy (EIS) is traditionally used to characterize electrode surfaces, for applications including corrosion monitoring or characterizing the fouling of implanted electrodes.

It is also possible to use EIS to monitor the growth of adherent cells on surfaces or to estimate the surface coverage of bacterial biofilms. At larger dimensions, this approach has been commercialized in impedance-based cell culture monitoring systems, which use millimeter-scale interdigitated electrodes.

These examples use EIS for monitoring cells in extremely close contact with the electrode because mobile dissolved ions in the buffer form an electrostatic double layer at the surface with very high charge density. This Debye layer screens the electric field from penetrating more than a few nanometers into a sample. However, the relaxation time of the screening layer is on the order of 1 μs, and at MHz frequencies the electric field can extend farther into a sample. Radiofrequency EIS offers opportunities for imaging thicker samples or non-adherent cells. Operating at higher frequencies also makes an impedance measurement less dependent on the exact surface charge, which is prone to drift.

Biologists often image cells and microorganisms using phase contrast modes, taking advantage of the difference in dielectric properties between cells and their surroundings. EIS imaging can similarly observe changes in local dielectric properties, such as water displaced by a cell crowded with lipids, proteins, and other molecules. Under some conditions, impedance imaging can detect and localize conductivity changes more than 100 μm from the electrode surface.

Impedance Imaging of Single-Celled Algae

To illustrate some of the types of microbial imaging that can be done using electrochemical sensors, we measured a variety of unicellular algae using a high-frequency EIS CMOS sensor array. The operating principle of the sensor is similar to those described elsewhere. Briefly, the sensor contains a grid of electrodes with a pitch of approximately 10 μm. Each electrode can be rapidly charged and discharged between two bias voltages, while the net current is measured (FIG. 16). The switching frequency can operate as fast as 100 MHz, and the charge transferred per cycle is a function of the interfacial capacitance (alternatively expressed in terms of impedance) between the metal electrode and the wet sample on its surface. A silver/silver-chloride reference electrode maintains the solution at a constant potential, although the measurement is typically not sensitive to the exact DC solution bias.

After assembling a small open fluid chamber around the sensor, we arranged the system under an inspection microscope (FIG. 16), for simultaneous optical and electrochemical visualization.

FIG. 17 shows measurements of filamentous freshwater green algae dispersed onto the surface of the sensor. There is strong correlation between the optical and impedance images, and the quality of the impedance image improves significantly at higher frequencies. Despite the improved sensing depth at radio frequencies, not all of the algae cells are detected in the impedance image. The rectangular cells have widths on the order of 20 μm, and they do not all lie flat on the sensor surface.

In FIG. 18 we see measurements of Cosmarium turpinii, a freshwater algae with a cell diameter of approximately 50 μm and a notable constriction in the middle. Individual cells are clearly detected by CMOS impedance imaging, although the subcellular structure is only sometimes observable. Cells with consistent and distinct shapes offer interesting test cases for evaluating the spatial resolution of CMOS biosensors.

FIG. 19 shows images of Closterium acerosum, another type of freshwater green algae which has crescent-shaped cells with tapered ends. These larger cells are very clearly resolved, though on occasion we can see some loss of contrast as part of the cell appears to extend farther from the sensor surface.

Smaller microalgae are more challenging to detect. FIG. 20 shows measurements of Cyclotella sp., which are round and flat marine diatoms with diameters close to the size of the 10 μm sensor pixels. Some of these cells are clearly detected, but they appear primarily as single points in the EIS image.

Impedance images can be resolved temporally as well as spatially. Closterium (FIG. 19) can move by secreting mucilage to push away from objects in their environment. FIG. 21 shows snapshots from a 1.5 hour impedance timelapse movie, in which single Closterium cells can be seen moving laterally across the sensor and vertically in and out of the sensing volume. Visualizing the kinetics of cellular growth and motion offer another opportunity for characterizing and identifying microorganisms.

Clearly any natural environment will present mixtures of species, rather than pure cultures. FIG. 22 shows a mixture of Cosmarium and Closterium algae cells dispersed onto an EIS array. Even with this simple mixture, we can begin to appreciate the challenge of not merely detecting cells, but also classifying them.

In FIG. 23, we show an example from a dataset in which cells were segmented from the background, and a classifier was trained on images of pure Cosmarium and Closterium cells. The classification was based on two simple shape metrics, cell area and aspect ratio. This classifier was then applied to a mixed sample, where it was able to successfully label a large majority of the cells. Most of the errors occurred when Closterium cells were tilted out of the sensing plane and mistaken for smaller Cosmarium cells. Automated phenotype classification from microscopy data is an exciting and active area of research, and as the spatial resolution of electrochemical images improves, there will be more opportunities for applying machine learning to these rich datasets.

It would be appreciated by those skilled in the art that various changes and modifications can be made to the illustrated embodiments without departing from the spirit of the present invention. All such modifications and changes are intended to be within the scope of the present invention except as limited by the scope of the appended claims.

Claims

1. A complementary metal-oxide-semiconductor sensor array comprising: an active sensing area of pixels arranged in a regular array, each pixel comprising an exposed surface electrode alongside switches and logic gates; andnon-overlapping clocks configured to rapidly charge and discharge the exposed surface electrode within each pixel,wherein control signals steer a switched output current between shared differential column outputs.

2. The complementary metal-oxide-semiconductor sensor array of claim 1 wherein the active sensing area of pixels comprises 4,096 pixels.

3. The complementary metal-oxide-semiconductor sensor array of claim 2 wherein the 4,096 pixels are arranged in a 64×64 array with a 10 micron pitch.

4. The complementary metal-oxide-semiconductor sensor array of claim 3 wherein there are two non-overlapping clocks.

5. The complementary metal-oxide-semiconductor sensor array of claim 4 wherein there are four switches and two logic gates.

6. The complementary metal-oxide-semiconductor sensor array of claim 5 wherein there are two control signals and two shared column outputs.

7. The complementary metal-oxide-semiconductor sensor array of claim 1 wherein the two shared column outputs are directed into a high-bandwidth differential current buffer, followed by a pair of integration capacitors, and a pair of output buffers.

8. The complementary metal-oxide-semiconductor sensor array of claim 7 wherein a differential output voltage is digitized by a 16-bit PCI data acquisition card.

9. An ion-sensitive field-effect transistor (ISFET) circuit comprising: an array of ion-sensitive field-effect transistor pixels, each pixel comprising a first PMOS transistor and a second PMOS transistor, the first PMOS transistor acting as a sensing ISFET and the second PMOS transistor acting as a reference MOSFET; anda readout circuit.

10. The ion-sensitive field-effect transistor (ISFET) circuit of claim 9 wherein the array is a 6×6 array.

11. The ion-sensitive field-effect transistor (ISFET) circuit of claim 9 wherein the array comprises pixels designed with silicon nitride (Si3N4) or TiN surfaces.

12. The ion-sensitive field-effect transistor (ISFET) circuit of claim 9 wherein the readout circuit comprises: a voltage-clamped current buffer;a programmable-gain transimpedance amplifier; anda voltage buffer.

13. The ion-sensitive field-effect transistor (ISFET) circuit of claim 12 wherein the readout circuit further comprises: a second order anti-aliasing filter; anda 16-bit data acquisition card.

14. The ion-sensitive field-effect transistor (ISFET) circuit of claim 13 wherein the voltage-clamped current buffer comprises a common-gate amplifier with gain boosting.

15. The ion-sensitive field-effect transistor (ISFET) circuit of claim 14 wherein 6×6 array of ion-sensitive field-effect transistor pixels employs a balanced PMOS switching method wherein two phases are balanced to not change the electrode surface potential in the two phases.

16. A complementary metal-oxide-semiconductor sensor array comprising: an active sensing area comprising pixels arranged in an array, each pixel comprising:an exposed surface electrode;a high-frequency impedance circuit;an nMOS ISFET configured for pH sensing; anda photodetector.

17. The complementary metal-oxide-semiconductor sensor array of claim 16 wherein the active sensing area comprises 131,072 pixels arranged in a 512×256 array.

18. The complementary metal-oxide-semiconductor sensor array of claim 16 wherein a current is steered between two shared column outputs using a set of control signals.

19. The complementary metal-oxide-semiconductor sensor array claim 18 wherein the set of control signals comprises a first control signal and a second control signal.

20. The complementary metal-oxide-semiconductor sensor array claim 19 wherein a configuration of the first control signal enables a readout supporting time-division multiplexing (TDM) or code-divisional multiplexing (CDM).

21. The complementary metal-oxide-semiconductor sensor array of claim 16 wherein the photodetector comprises a plurality of photodiodes configured for optical imaging.

22. The complementary metal-oxide-semiconductor sensor array of claim 16 wherein the plurality of photodiodes comprises three diodes.

23. The complementary metal-oxide-semiconductor sensor array of claim 22 wherein the three diodes share a same P-substrate but have isolated N-well cathode contacts that are biases to V0, V1 and V2.

24. The complementary metal-oxide-semiconductor sensor array of claim of claim 18 wherein the column outputs are directed into a high-bandwidth different current buffer.

25. A system comprising: a CMOS sensor array that uses a two-phase switching scheme to measure the mutual capacitance between pairs of nearby pixels.

26. The system of claim 25 wherein array comprises 10,000 pixels.

27. The system of claim 26 wherein each pixel can be driven by one of two pairs of non-overlapping input clocks, whose relative phases are synthesized by an external delay lock loop.

28. The system of claim 27 wherein a set of control signals drive each row and column to determine a clock selection in each pixel.

29. The system of claim 28 wherein an output current of each pixel is routed to a readout circuit.

30. The system of claim 29 wherein the readout circuit comprises chopping switches and a pair of integrators for signal amplification, followed by buffers that drive an external 500 kS/s 18-bit ADC.

31. The system of claim 30 wherein differential chopping and correlated double-sampling are used to suppress the 1/f noise and offsets.

32. A system comprising: a high-density CMOS microelectrode array that can manipulate fringe fields of a pixel during electrochemical impedance measurements by configuring clock phases and bias voltages within a moving kernel of neighboring pixels.

33. The system of claim 32 wherein the array comprises 10 μm×10 μm pixels.

34. The system of claim 32 wherein the pixels are driven by non-overlapping switching clocks with different phase offsets and biased by different output voltages.

35. A system comprising: a CMOS sensor array that uses a two-phase switching scheme to measure the mutual capacitance between pairs of nearby pixels, wherein the switching scheme further comprises: switches within each pixel to charge and discharge between two voltages digital logic to independently select two pixels from the array circuitry to apply different phase clocks to each of the two pixels circuitry to route one pixel to a readout integratorall together, resulting in the ability to configure any two pixels to be equivalent to a non-inverting switched-capacitor integrator.