Patent Application
20250192049
The present disclosure generally relates to transistors, and more particularly, to the bipolar devices and backside power delivery networks, and methods of creation thereof.
Bipolar junction transistors (BJTs) are semiconductor devices used in electronic circuits for various purposes, including amplification, switching, and signal processing. They usually come in two types: NPN (negative-positive-negative) and PNP (positive-negative-positive). Typically, BJTs include three layers of semiconductor material, namely the emitter, base, and collector. The flow of current between the emitter and collector is controlled by a small current applied to the base terminal. In some applications, NPN BJTs amplify current, while PNP BJTs amplify voltage. BJTs are known for their high gain and fast switching capabilities, making them salient components in various electronic applications, including amplifiers, digital logic gates, and oscillators.
According to an embodiment, a semiconductor device includes a bipolar device, and a logic device adjacent the bipolar device. A frontside of the bipolar device is connected to a back end of line (BEOL), and a backside of the bipolar device is connected to a backside interconnect.
In some embodiments, which can be combined with the previous embodiment, the backside of the bipolar device is connected to the backside interconnect via a backside contact (BSCA) and a substrate.
In some embodiments, which can be combined with one or more previous embodiments, the frontside of the bipolar device is connected to the BEOL via a plurality of source/drain regions and a middle of line (MOL) contact.
In some embodiments, which can be combined with one or more previous embodiments, the bipolar device further comprises a substrate. The plurality of source/drain regions are P-doped, and the substrate is N-doped.
In some embodiments, which can be combined with one or more previous embodiments, the bipolar device further comprises a substrate. The plurality of source/drain regions are N-doped, and the substrate is P-doped.
In some embodiments, which can be combined with one or more previous embodiments, the semiconductor further includes a diffusion break between two adjacent source/drain regions. A bottom of the diffusion break is isolated from a substrate by a self-aligned substrate isolation (SASI).
In some embodiments, which can be combined with one or more previous embodiments, the semiconductor device includes a plurality of field-effect transistors (FETs).
In some embodiments, which can be combined with one or more previous embodiments, a first source/drain region in a first FET in the logic device is connected to the backside interconnect via the BSCA.
In some embodiments, which can be combined with one or more previous embodiments, the BSCA in the logic device includes a self-aligned portion and a non-self-aligned portion.
In some embodiments, which can be combined with one or more previous embodiments, the semiconductor further includes a layer of first inner spacer over portions of sidewalls of the self-aligned portion of the BSCA.
In some embodiments, which can be combined with one or more previous embodiments, a second source/drain region in a second FET in the logic device is connected to the BEOL via a MOL contact.
In some embodiments, which can be combined with one or more previous embodiments, the semiconductor device further includes a placeholder connected to the second source/drain region, and a layer of a second inner spacer over portions of sidewalls of the placeholder.
According to an embodiment, a method for forming a semiconductor device includes forming a bipolar device, providing a connection between a frontside of the bipolar device to a back end of line (BEOL), providing a connection between a backside of the bipolar device to a backside interconnect, and forming a logic device adjacent the bipolar device.
In some embodiments, which can be combined with the previous embodiment, the method includes providing a connection between the frontside of the bipolar device to the BEOL via a plurality of source/drain regions and a middle of line (MOL) contact.
In some embodiments, which can be combined with one or more previous embodiments, the method includes providing a connection between the backside of the bipolar device to the backside interconnect via a backside contact (BSCA) and a substrate.
In some embodiments, which can be combined with one or more previous embodiments, the method includes forming a diffusion break between two adjacent source/drain regions, and isolating a bottom of the diffusion break from the substrate by a self-aligned substrate isolation (SASI).
In some embodiments, which can be combined with one or more previous embodiments, the method includes providing a connection between a source/drain region in the logic device and the backside interconnect via the BSCA.
In some embodiments, which can be combined with one or more previous embodiments, the method includes forming a placeholder connected to a source/drain region, and forming a layer of inner spacer over portions of sidewalls of the placeholder.
In some embodiments, which can be combined with one or more previous embodiments, the method includes providing a connection between a source/drain region in the logic device and the BEOL via a MOL contact.
According to an embodiment, a semiconductor device includes a bipolar device, wherein a backside of the bipolar device is connected to a backside interconnect, a logic device adjacent the bipolar device, a backside contact (BSCA) in the logic device having a self-aligned section and a non-self-aligned section, and an inner spacer over sidewalls of the self-aligned section of the BSCA.
These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps.
In the following detailed description, numerous specific details are set forth by way of examples to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, to avoid unnecessarily obscuring aspects of the present teachings.
In one aspect, spatially related terminology such as “front,” “back,” “top,” “bottom,” “beneath,” “below,” “lower,” above,” “upper,” “side,” “left,” “right,” and the like, is used with reference to the orientation of the Figures being described. Since components of embodiments of the disclosure can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. Thus, it will be understood that the spatially relative terminology is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
As used herein, the terms “lateral” and “horizontal” describe an orientation parallel to a first surface of a chip.
As used herein, the term “vertical” describes an orientation that is arranged perpendicular to the first surface of a chip, chip carrier, or semiconductor body.
As used herein, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together-intervening elements may be provided between the “coupled” or “electrically coupled” elements. In contrast, if an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. The term “electrically connected” refers to a low-ohmic electric connection between the elements electrically connected together.
Although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope.
It is to be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.
As used herein, certain terms are used indicating what may be considered an idealized behavior, such as, for example, “lossless,” “superconductor,” or “superconducting,” which are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss or tolerance may be acceptable such that the resulting materials and structures may still be referred to by these “idealized” terms.
The concepts herein are related to bipolar junction transistors (BJTs), which are semiconductor devices that can be used in BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor) technology, where it coexists harmoniously with CMOS (Complementary Metal-Oxide-Semiconductor) logic gates within a single integrated circuit. BJTs are known for their high-speed operation, high gain, and low output impedance, and are typically used in analog and high-frequency applications where amplification and signal fidelity are critical. BJTs are often used for applications such as analog amplifiers and low-noise radio frequency (RF) circuits due to their fast switching characteristics. CMOS technology, on the other hand, is renowned for its low-power consumption, high input impedance, and suitability for digital logic circuits. CMOS is a salient component of the digital electronics, offering energy-efficient operation and the ability to construct large arrays of logic gates for digital signal processing.
In a BiCMOS chip, the two technologies are integrated in a complementary manner. This means that BJTs handle analog functions that involve high-speed, high-gain amplification, while CMOS components are used for digital logic, which benefits from low power consumption and compatibility with large-scale integration. BiCMOS technology is particularly valuable in mixed-signal applications, where both analog and digital circuitry coexist on the same chip. Examples of applications that benefit from BiCMOS technology include data converters (analog-to-digital and digital-to-analog converters), wireless communication systems, precision analog circuits, and high-performance microcontrollers.
As mentioned earlier, BJTs exhibit high-speed operation, providing rapid switching capabilities ideal for applications requiring quick signal amplification or modulation. Moreover, BJTs offer high voltage gain, making them valuable components in amplifiers where signal fidelity and precision are paramount. Their low output impedance ensures efficient power transfer, which is especially advantageous in scenarios demanding robust signal transmission. However, it is worth noting that BJTs tend to consume relatively more power per device compared to CMOS components.
In contrast, CMOS devices inherently boast high input impedance, which minimizes loading effects and enhances signal integrity. Additionally, CMOS is adept at constructing large arrays of low-power logic gates. This makes CMOS the technology of choice for designing energy-efficient digital circuits and processors. The combination of BJTs and CMOS in BiCMOS technology leverages the high-speed, high-gain, and low output impedance of BJTs while harnessing the high input impedance and low power consumption attributes of CMOS logic gates.
One key application domain where this synergy shines is in the realm of high-frequency analog amplification, particularly in the development of low-noise RF amplifiers, where the judicious use of BJTs within the BiCMOS framework allows designers to achieve the required signal amplification with precision and minimal noise interference. The employment of a select few active devices optimizes power consumption while still delivering high-performance RF amplification. This is a testament to the versatility and adaptability of BiCMOS technology in catering to the diverse demands of modern electronics, where high-frequency analog amplification meets low-power, high-density logic gate integration.
While backside power delivery network (BSPDN) formation, including schemes such as direct backside source/drain contact, offers advantages in certain semiconductor applications, integrating bipolar devices, such as BJTs, with logic circuits in this context presents numerous intricate challenges. These challenges encompass complexities associated with substrate removal, considerations related to thermal and mechanical effects, isolation and signal compatibility prerequisites, power supply management, and comprehensive testing and validation efforts. Addressing these challenges effectively is essential to achieving the successful integration of bipolar and CMOS devices in semiconductor fabrication.
In view of the foregoing, disclosed is a semiconductor device that integrates BJTs with direct backside contact and with accurate backside contact depth control. The disclosed semiconductor device enables PSPDN formation for a bipolar device, such as a BJT, which is cointegrated with a logic device.
Accordingly, the teachings herein provide methods and systems of semiconductor device formation with integrated BSPDN. The techniques described herein may be implemented in a number of ways. Example implementations are provided below with reference to the following figures.
Example Semiconductor Device with Integrated BSPDN Structure
Reference now is made to
The bipolar device 110B includes an emitter 142, a base 144, and a collector 146. In some embodiments, while the emitter 142 can be a third source/drain region 152, the collector can be a fourth source/drain region 156, and the base can be a doped substrate 154. The bipolar device 110B can further include a second contact 166A, a third contact 166B, a second backside contact, BSCA, 170, the SASI 128, and a diffusion break dielectric, 172. Similar to the logic device 110A, the bipolar device 110B is connected to the backside interconnect 134 on a backside, and to the BEOL 136 and the carrier wafer 138 on a frontside. The second contact 166A can include, or be resistively coupled to, an emitter electrode. The third contact 166B can include, or be resistively coupled to, a collector electrode.
Generally, the first source/drain region 114A, the second source/drain region 114B, the third source/drain region 152, and the fourth source/drain region 156 are salient components that play relevant roles in the semiconductor device's operation. In various embodiments, the first source/drain region 114A, the second source/drain region 114B, the third source/drain region 152, and the fourth source/drain region 156 are regions within the semiconductor material, e.g., the semiconductor device 100, where the current flows in and out of the semiconductor device 100. The source region is the region through which the majority of charge carriers (e.g., electrons or holes) enter the channel of the semiconductor device and is responsible for providing the current that flows through the semiconductor device. The source region is typically doped to have an excess of charge carriers, creating a region with high carrier concentration. This abundance of carriers allows for the efficient injection of electrons or holes into the channel when a voltage is applied.
The drain region, on the other hand, is the region where the majority of charge carriers exit the channel. The drain region receives the current from the channel and carries the charge away from the transistor. Similar to the source, the drain region is also doped to have a high carrier concentration. The doping profile in the drain region ensures that carriers can easily flow out of the channel and into the drain region.
In some embodiments, the first source/drain region 114A is connected to a frontside of the semiconductor device 100 via the first contact 116A. In some embodiments, a gate region is connected to the frontside of the semiconductor device 100 via the ILD 130. In an embodiment, the second source/drain region 114B is connected to the backside of the semiconductor device 100 via the BSCA 120.
The first contact 116A, located over the first source/drain region 114A, establishes a connection between the first source/drain region 114A and the BEOL 136. The first contact 116A ensures efficient electrical routing and connectivity within the semiconductor device 100. The fabrication of the first contact 116A can involve lithography and etching processes to define the contact area. The first contact 116A can be made using conductive materials such as a silicide liner, e.g., Ni, Ti, NiPt, an adhesion metal layer, e.g., TiN and conductive metal fill material, e.g., tungsten (W), Co, or Ru.
The first set of nanosheets 118 includes 3D structures where the channel region of the logic device 110A is surrounded by multiple stacked nanosheets. The first set of nanosheets 118 serve as the conducting channels within the logic device 110A, and the gate structure controls the flow of current through these sheets.
The BSCA 120 is a region on the backside of the semiconductor device 100 where electrical connections are made. By establishing the electrical contacts, the BSCA 120 ensures the proper functioning of the semiconductor device 100 and facilitates electrical signal transmission.
The BSCA 120 can serve as a thermal interface between the semiconductor device 100 and a heat sink or other cooling mechanisms. By establishing direct contact with the substrate, the BSCA 120 can conduct the heat away from the semiconductor device 100, and contribute to improved thermal dissipation. In some embodiments, the BSCA 120 can help mitigate parasitic effects, such as substrate coupling or substrate noise, from the semiconductor device 100. The BSCA 120 can allow for increased integration density in the semiconductor device 100. In an embodiment, the BSCA 120 connects, i.e., wires, the second source/drain region 114B to the backside interconnect 134.
In some embodiments, the BSCA 120 includes an upper section 160A and a lower section 160B. The upper section 160A is connected to the second source/drain region and is self-aligned with respect to the second source/drain region 114B. As such, the upper section 160A has a width that is substantially equal to the width of the second source/drain region 114B. The lower section 160B connects the upper section 160A to the backside interconnect 134, and is not self-aligned with the second source/drain region 114B. As such, the lower section 160B has a width that is larger than the width of the upper section 160A. In some embodiments, the inner spacer 126 touches, i.e., covers, parts of the upper section 160A, i.e., the self-aligned portion, of the BSCA 120. In some embodiments, the inner spacer 126 is formed over the upper surface of the lower section 160B of the BSCA 120.
In various embodiments, the gate region 122 serves as control elements that regulate the flow of current through the semiconductor device 100. The gate region 122 can comprise a conductive material. The gate region 122 can control the flow of electric current between the source and drain regions. In some embodiments, by applying a voltage to the gate, the channel region's conductivity is modulated, allowing the semiconductor device 100 to either allow or block the flow of current, which in turn enables the semiconductor device 100 to act as electronic switches or amplifiers. The gate voltage can determine whether the semiconductor device 100 is in an “on” or “off” state. When the gate voltage is below a certain threshold, the semiconductor device 100 is in the “off” state, and the current flow between the source and drain is effectively blocked. On the other hand, when the gate voltage exceeds the threshold, the semiconductor device 100 enters the “on” state, allowing current to flow through the channel region. In addition to acting as a switch, modulating the gate voltage can enable the gate region 122 to control the current flowing through the channel region, resulting in amplified output signals.
In an embodiment, the gate region 122 can enable the implementation of Boolean logic operations, such as AND, OR, and NOT, by controlling the flow of current based on the input voltages. Multiple semiconductor devices can be interconnected to form complex logic circuits, enabling the execution of various computational tasks in digital systems. In some embodiments, the gate region 122, along with other semiconductor device components, can facilitate the miniaturization and integration of electronic circuits. The ability to control the channel region's conductivity through the gate voltage allows for compact and highly efficient circuit designs.
In some embodiments, the placeholder 124 can be epitaxially grown. The use of the placeholder 124 can provide more flexibility in the fabrication process, allowing for the creation of complex geometries or the integration of different types of materials.
The first inner spacer 126 can be formed over portions of sidewalls of the placeholder 124 and the BSCA 120. To that end, the first inner spacer 126 is formed within the etch stop layer, which is shown as “etch stop layer 210” in
The SASI 128 can be utilized to isolate the semiconductor structure from the substrate electrically, and provide isolation and reduce parasitic capacitance and leakage currents between the semiconductor device 100 and the substrate. The SASI 128 is a dielectric material that can help improve the semiconductor device 100 performance and reliability by minimizing undesirable effects such as substrate leakage and latch-up.
The ILD 130 can be a layer of insulating material to electrically isolate and provide mechanical support between different layers of conducting and active components. The ILD 130 can enable efficient signal transmission, reduce crosstalk, and ensure the proper functioning of the semiconductor device 100. In an embodiment, the ILD 130 can electrically isolate adjacent conducting layers or active components in the semiconductor device 100. By providing insulation between different layers, the ILD 130 can prevent electrical shorts, reduce (e.g., minimize) leakage current, and ensure that signals are directed only along the desired pathways. In some embodiments, the ILD 130 can help reduce parasitic capacitance between adjacent metal interconnects or active devices and provide mechanical support to the semiconductor device's structure.
The BILD 132 can be an insulating material or layer used to isolate and provide electrical insulation between the semiconductor device's active regions and the BSCA 120, and to prevent unwanted electrical contact between the active regions and the backside contact, ensuring the proper functioning and integrity of the semiconductor device 100. In various embodiments, the BILD 132 can function as a protective layer, shielding the active regions of the semiconductor device 100 from external contaminants, moisture, and mechanical stress. The BILD 132 can further help prevent physical damage, such as scratches or particle contamination, which could adversely affect semiconductor device performance. Additionally, the BILD 132 can function as a barrier against moisture ingress, which can cause corrosion and degradation of the semiconductor device's components. In some embodiments, the backside interconnect 134 is formed to cover the BSCA 120 and the BILD 132. The backside interconnect 134 can connect the semiconductor device 100 to other devices.
The BEOL 136 includes metal interconnects, e.g., wires and metal lines, and insulating layers that connect the various components of the semiconductor device 100 and enable them to function as a cohesive unit. In some embodiments, one or more source/drain regions in the logic device 110A, e.g., the first source/drain region 114A, is connected to the BEOL 136 via the first contact 116A. In such embodiments, the bottom of the source drain region, e.g., the first source/drain region 114A, is connected to the placeholder 124.
The emitter 142 can be heavily doped n-type or p-type, to provides excess carriers. In some embodiments, the emitter 142 can act as source of charge carriers that provide most of emitter-collector current. The base 144 can be lightly doped, compared to the emitter 142, with opposite type from the emitter 142. That is, if the emitter is p-type, then the base 144 is n-type, and vice versa. In an embodiment, the base 144 has a thin width which allows carriers from the emitter 142 to diffuse across the base 144 and reach the collector 146. In various embodiments, while the base-emitter junction is forward biased, the base-collector junction is reverse biased. The collector 146 is moderately doped, compared to the emitter 142 and the base 144, with the same type as the emitter 142, and can collect carrier majority from the emitter 142, causing the emitter-collector current.
As shown in
The second contact 166A, located over the third source/drain region 152, establishes a connection between the third source/drain region 152 and the BEOL 136. The second contact 166A ensures efficient electrical routing and connectivity within the semiconductor device 100. The fabrication of the second contact 166A can involve lithography and etching processes to define the contact area. The second contact 166A can be made using conductive materials such as a silicide liner, e.g., Ni, Ti, NiPt, an adhesion metal layer, e.g., TiN and conductive metal fill material, e.g., tungsten (W), Co, or Ru.
Similarly, the third contact 166B, located over the fourth source/drain region 156, establishes a connection between the fourth source/drain region 156 and the BEOL 136. The third contact 166B ensures efficient electrical routing and connectivity within the semiconductor device 100. The fabrication of the third contact 166B can involve lithography and etching processes to define the contact area. The third contact 166B can be made using conductive materials such as a silicide liner, e.g., Ni, Ti, NiPt, an adhesion metal layer, e.g., TiN and conductive metal fill material, e.g., tungsten (W), Co, or Ru.
The BSCA 170 is a region on the backside of the bipolar device 110B where electrical connections are made. By establishing the electrical contacts, the BSCA 170 ensures the proper functioning of the bipolar device 110B and facilitates electrical signal transmission.
The BSCA 170 can serve as a thermal interface between the bipolar device 110B and a heat sink or other cooling mechanisms. By establishing direct contact with the substrate, the BSCA 170 can conduct the heat away from the bipolar device 110B, and contribute to improved thermal dissipation. In some embodiments, the BSCA 170 can help mitigate parasitic effects, such as substrate coupling or substrate noise, from the bipolar device 110B. In further embodiments, the BSCA 170 can allow for increased integration density in the bipolar device 110B.
The diffusion break dielectric 172 is an insulating layer that separates the third source/drain region 152 and the fourth source/drain region 156, and can be made from silicon dioxide or silicon nitride. The diffusion break dielectric 172 can reduce minority carrier injection and improve current gain.
In some embodiments, the bipolar device 110B is a bipolar junction transistor (BJTs), which can be used for amplification and switching. BJT is a three-layer semiconductor device that functions as an electronic switch or amplifier. While in some embodiments, the BJT is a Negative-Positive-Negative, NPN, device, in some embodiments, the BJT is a Positive-Negative-Positive, PNP, device. Each of the NPN and PNP can function as a switch, in which by controlling the current applied to the base terminal, they can control the larger current flowing from the collector to the emitter, effectively using the transistor as an electronic switch.
In some embodiments, the bipolar device 110B is used as an amplifier. In such embodiments, in the amplification mode (active region), a small input current or voltage is applied at the base terminal to control a larger current flow between the collector and emitter.
In some embodiments, the passive device's configuration is a common emitter (NPN) or common base (PNP) configuration. In such a configuration, the input is applied to the base terminal, and the output is taken from the collector terminal, which provides voltage gain. Alternatively, in some embodiments, the passive device's configuration is a common collector (NPN) or common emitter (PNP) configuration. In such a configuration, the input is applied to the base terminal, and the output is taken from the emitter terminal, which provides current gain and is sometimes called an emitter follower.
Example Processes for Bipolar Device with Integrated BSPDN
With the foregoing description of an example semiconductor device, it may be helpful to discuss an example process of manufacturing the same. To that end,
Reference is now made to
In various embodiments, the first substrate 210A may include any suitable material or combination of materials, such as doped or undoped silicon, glass, dielectrics, etc. For example, the substrate may include a silicon-on-insulator (SOI) structure, e.g., with a buried insulator layer, or a bulk material substrate, e.g., with appropriately doped regions, typically referred to as wells. In another embodiment, the substrate may be silicon with silicon oxide, nitride, or any other insulating film on top.
In various embodiments, the etch stop layer 210 is formed over the first substrate 212A. The etch stop layer 210 can be a thin layer of material incorporated into the structure of the semiconductor device to provide a selective barrier against etching processes, preventing further removal of underlying materials during fabrication. The etch stop layer 210 can enable precise control over the etching depth and help define the desired device dimensions. The etch stop layer 210 can further provide a stopping point for the etching process, ensuring that specific layers or regions are not etched beyond a certain point, leading to accurate patterning and control of critical features. The etch stop layer 210 can create a distinct separation between different layers or components within the device structure, and prevent the undesired etching of underlying layers or materials, enabling the creation of complex, multi-layered structures with well-defined interfaces and boundaries. In some embodiments, the etch stop layer 210 acts as a protective barrier for sensitive or delicate materials to shield such materials from aggressive etchants, preventing damage or degradation during subsequent fabrication steps.
In some embodiments, prior to forming the etch stop layer 210, the first substrate 212A is prepared by cleaning and removing any impurities or oxide layers. The etch stop layer 210 is deposited onto the first substrate 212A using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In an embodiment, a photoresist can be applied, exposed to a patterned mask, developed, and used as a protective layer to define the etch stop regions. The etch stop layer 210 can then be selectively etched, stopping at a predetermined depth, while protecting the underlying layers. After the etching process, the remaining photoresist can be removed through stripping techniques. While in some embodiments, SiGe is used to form the etch stop layer 210, in some embodiments, silicon nitride (SiN), silicon oxide (SiO2), or silicon oxynitride (SiON) can be used as the etch stop layer 210. In some embodiments, a second substrate, substrate 212B, is epitaxially grown over the etch stop layer 210. The substrate 212B can be an N-well substrate.
The inner pacer 216 is formed over the sidewalls of the placeholder 224 and the sacrificial placeholder 226 in the logic device 202B. The placeholder 224 and the sacrificial placeholder 226 can be made of Sic or epitaxially grown <100> SiGe. In some embodiments, a dummy gate 218 is formed over the logic device 202B and the bipolar device 202A. One or more source/drain regions 220 are epitaxially formed between the nanosheets 222, which are formed by recessing alternating layers of Si and SiGe. The SASI 238 is formed over the second substrate 210B and isolates the N-well substrate from damage during various fabrication acts.
In various embodiments, carrier wafer bonding, also known as wafer-to-wafer bonding or chip-to-wafer bonding, is performed to join two semiconductor devices together by creating a permanent bond between them. In some embodiments, the two semiconductor devices can be brought into contact and bonded at the atomic or molecular level, to create an interface. In an embodiment, the two semiconductor devices are brought into contact under controlled conditions, such as controlled pressure and temperature, to enable atomic or molecular bonding at the interface. Such bonding can be done at room temperature or with elevated temperatures. Alternatively, in some embodiments, an electric field and elevated temperature are utilized to create a bond. One semiconductor device can be made of semiconductor material, while the other can be a glass or silicon dioxide (SiO2) wafer. The electric field can cause ions in the glass or SiO2 to migrate and chemically bond with the semiconductor material in the other semiconductor device. In additional embodiments, a thin metal layer or metal alloy can be used as an intermediate bonding layer between the semiconductor devices. The metal layer can be deposited or transferred onto one or both semiconductor device surfaces, and the semiconductor devices can then be brought into contact and subjected to temperature and pressure to create a metallic bond.
As shown by block 1720, a connection between a frontside of the bipolar device to a back end of line (BEOL) is provided.
As shown by block 1730, a connection between a backside of the bipolar device to a backside interconnect is provided.
As shown by block 1740, a logic device is formed.
In one aspect, the method and structures described above may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip can then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from low-end applications, such as toys, to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
While the foregoing has described what are considered to be the best state and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.
The components, steps, features, objects, benefits, and advantages that have been discussed herein are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.
Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently.
While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term “exemplary” is merely meant as an example, rather than the best or optimal. Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.
It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or implying any actual relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “a” or “an” does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, the inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
