Claims
- 1. An IED comprising:
a power monitoring circuit operative to monitor a parameter of a portion of a power distribution system and generate an analog signal representative thereof; a processor coupled with said power monitoring circuit and operative to receive said analog signal and at least one of quantify and report said monitored parameter, said processor further including an integrated circuit, said integrated circuit comprising:
a non-volatile memory operative to store program code for said processor; a digital processing core coupled with said non-volatile memory and operative to execute said stored program code to implement said quantifying and reporting functions; and a volatile memory coupled with said processing core and operative to store working data code for said digital processing core during execution of said stored program code.
- 2. The IED of claim 1, wherein said non-volatile memory comprises a flash memory.
- 3. The IED of claim 1, wherein said non-volatile memory further comprises a boot portion, a program portion and a data portion.
- 4. The IED of claim 3, wherein said boot portion is separately eraseable from said program and data portions.
- 5. The IED of claim 3, wherein said data portion is further sectioned into a plurality of data segments.
- 6. The IED of claim 1, wherein said volatile memory comprises a static RAM memory.
- 7. The IED of claim 1, wherein said digital processing core further comprises and an analog to digital converter operative to receive said analog signal and generate a digital signal representative thereof.
- 8. The IED of claim 1, wherein said integrated circuit further comprises an operating power detection circuit operative to monitor operating power delivered to said IED by an operating power supply of said IED and generate a signal to said digital processing core when said operating power falls below a threshold, said digital processing core further operative to transfer at least a portion of said stored working data from said volatile memory to said non-volatile memory upon receipt of said signal.
- 9. The IED of claim 8, further comprising a back-up power supply coupled with said processor and responsive to said signal, said back-up power supply operative to supply power to said processor when said signal is received to facilitate said transfer.
- 10. The IED of claim 9, wherein said back-up power supply comprises a capacitor.
- 11. The IED of claim 8, wherein said operating power supply is operative to supply a first voltage for operating said IED and a second voltage for operating said processor, and wherein said operating power supply further comprises a resistive divider operative to generate a third voltage for said operating power detection circuit.
- 12. The IED of claim 11, wherein said first voltage is substantially equivalent to 5 volts DC, said second voltage is substantially equivalent to 3.3 volts DC and said third voltage is substantially equivalent to 2.5 volts DC.
- 13. The IED of claim 8, wherein said operating power detection circuit comprises an analog to digital converter.
- 14. A method for storing working data code for an IED, the method comprising:
monitoring a parameter of a portion of a power distribution system and generating an analog signal representative thereof; receiving said analog signal and at least one of quantifying and reporting said monitored parameter; storing a program code for a processor in a non-volatile memory, wherein said processor comprises said non-volatile memory, a volatile memory and a digital processing core; executing said stored program code to implement said quantifying and reporting functions; and storing, with said volatile memory, working data code for said digital processing core during execution of said stored program code, wherein said volatile memory couples with said processing core.
- 15. The method of claim 14 wherein said non-volatile memory comprises a flash memory.
- 16. The method of claim 14, wherein said non-volatile memory further comprises a boot portion, a program portion and a data portion.
- 17. The method of claim 16, wherein said boot portion is separately eraseable from said program and data portions.
- 18. The method of claim 16, wherein said data portion is separately eraseable from said program and boot portions.
- 19. The method of claim 16, wherein said data portion is further sectioned into a plurality of data segments.
- 20. The method of claim 14, wherein said volatile memory comprises a static RAM memory.
- 21. The method of claim 14, further including receiving said analog signal and generating a digital signal representative thereof.
- 22. The method of claim 14, further comprising:
monitoring operating power delivered to said IED by an operating power supply of said IED and generating a signal to the digital processing core when said operating power falls below a threshold; and transferring at least a portion of said stored working data from said volatile memory to said non-volatile memory upon receipt of said signal.
- 23. The method of claim 22, further comprising supplying power to a processor with a back-up power supply when said signal is received to facilitate said transfer.
- 24. The method of claim 23, wherein said back-up power supply comprises a capacitor.
- 25. The method of claim 22, further comprising supplying a first voltage for operating said IED and a second voltage for operating a processor, and wherein said operating power supply comprises a resistive divider operative to generate a third voltage for an operating power detection circuit.
- 26. The method of claim 25, wherein said first voltage is substantially equivalent to 5 volts DC, said second voltage is substantially equivalent to 3.3 volts DC and said third voltage is substantially equivalent to 2.5 volts DC.
- 27. The method of claim 23, wherein said operating power delivered to said IED by said operating power supply of said IED is monitored using an operating power detection circuit.
- 28. The method of claim 27 wherein said operating power detection circuit comprises an analog to digital converter.
REFERENCE TO EARLIER FILED APPLICATIONS AND RELATED APPLICATIONS
[0001] The present application claims the benefit of U.S. application Ser. No. 09/791,421 filed Feb. 23, 2001, which is incorporated by reference herein.
[0002] The following co-pending and commonly assigned U.S. Patent Applications have been filed on the same date as the present application. These applications relate to and further describes other aspects of the embodiments disclosed in the present application and are herein incorporated by reference.
[0003] U.S. patent application Ser. No. ______, “EXPANDABLE INTELLIGENT ELECTRONIC DEVICE”, (Attorney Ref. No. 6270/66), filed concurrently herewith.
[0004] U.S. patent application Ser. No. ______, “APPARATUS AND METHOD FOR SEAMLESSLY UPGRADING THE FIRMWARE OF A INTELLIGENT ELECTRONIC DEVICE”, (Attorney Ref. No. 6270/68), filed concurrently herewith.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09791421 |
Feb 2001 |
US |
Child |
09931427 |
Aug 2001 |
US |