Number | Name | Date | Kind |
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4636813 | Mego et al. | Jan 1987 | |
5122693 | Honda et al. | Jun 1992 | |
5278466 | Honoa et al. | Jan 1994 | |
5280474 | Nickolls et al. | Jan 1994 |
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Menezes, Noel and Lawrence Pillage. Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. submitted for publication Feb. 2, 1995. |
Zhou et al., Interconnection Delay in Very High-Speed VLSI IEEE Transactions on Circuits and Systems, vol. 38, No. 7, Jul. 1991. |