Patent Application
20250237691
The present invention relates to integrated circuit design, and more specifically, to methods and structures for implementing interconnect process monitoring of interconnect wiring configurations of a chip design and identifying wire resistor-capacitator (RC) delay and capacitance parasitic characteristics for the interconnect wiring configurations of the chip design.
In integrated circuit (IC) or semiconductor chip designs, a significant challenge remains to provide effective interconnect wiring configurations in a given chip design. Current semiconductor chip designs continue to require smaller wiring sizes in wiring metallization layers and wiring layouts. Smaller wires increase wire resistance and denser wiring pitches cause higher coupling capacitance, which limit performance of the IC. New techniques and interconnect process monitor structures are needed that can enable effective and early identification of interconnect wiring issues and performance validation of interconnect wiring configurations in chip designs.
Disclosed embodiments provide methods, systems and computer program products for process monitoring of interconnect wiring configurations of semiconductor chip designs.
A disclosed computer implemented method comprises providing an interconnect process monitor structure comprising a plurality of latch stages coupled together, where each latch stage comprises a source latch, a buffered wire segment, a capture latch. The method comprises configuring the interconnect monitor structure to define wire and threshold voltage configurations for each respective buffered wire segment of the plurality of latch stages to represent a hardware interconnect wiring configuration for a chip design; scanning one or more test scan patterns into the interconnect monitor structure and capturing output test scan patterns from the interconnect monitor structure to determine wire Resistor-Capacitor (RC) parasitics of one or more buffered wire segments; and determining, based on the wire RC parasitics of the one or more buffered wire segments, performance behavior of the hardware interconnect wiring configuration for the chip design.
Other disclosed embodiments include a computer system and computer program product for implementing interconnect process monitoring of interconnect wiring configurations of a chip design, implementing features of the above-disclosed method.
The embodiments herein describe an interconnect monitor structure and techniques for interconnect wiring process monitoring and identifying interconnect wiring characteristics including AC wire resistor-capacitor (RC) characteristics and AC capacitance parasitics of a hardware interconnect wiring configuration of a chip design. A disclosed interconnect monitor structure includes multiple stages coupled together, each stage includes a source latch receiving test pattern data, a capture latch outputting test pattern data and a buffered wire segment coupled between the source latch and capture latch, which includes engineered wire configurations replicating the hardware interconnect wiring configuration of the chip design. The embodiments herein describe test pattern generation methods enabling efficient and effective wiring interconnect monitoring and identification of interconnect performance issues and validation of the hardware interconnect wiring configuration of a given IC design. The generated test patterns of disclosed embodiments applied to the interconnect monitor structure include a determined number of cycles of functional clocks to scan out test pattern data from one or more capture latches of one or more selected stages of the interconnect monitor structure that enables determining wire RC delay and capacitance parasitics of the selected stages. The disclosed embodiments enable early identification of metallization problems in interconnect wiring configurations, correlation of interconnect wiring RC characteristics to HW interconnect wiring configurations, for example, for enabling re-targeting interconnect wiring on higher metallization layers, and AC validation of wire RC paths.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
In the following, reference is made to embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice contemplated embodiments. Furthermore, although embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the scope of the present disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
Various aspects of the present disclosure are described by narrative text, flowcharts, block diagrams of computer systems and/or block diagrams of the machine logic included in computer program product (CPP) embodiments. With respect to any flowcharts, depending upon the technology involved, the operations can be performed in a different order than what is shown in a given flowchart. For example, again depending upon the technology involved, two operations shown in successive flowchart blocks may be performed in reverse order, as a single integrated step, concurrently, or in a manner at least partially overlapping in time.
A computer program product embodiment (“CPP embodiment” or “CPP”) is a term used in the present disclosure to describe any set of one, or more, storage media (also called “mediums”) collectively included in a set of one, or more, storage devices that collectively include machine readable code corresponding to instructions and/or data for performing computer operations specified in a given CPP claim. A “storage device” is any tangible device that can retain and store instructions for use by a computer processor. Without limitation, the computer readable storage medium may be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these mediums include: diskette, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded device (such as punch cards or pits/lands formed in a major surface of a disc) or any suitable combination of the foregoing. A computer readable storage medium, as that term is used in the present disclosure, is not to be construed as storage in the form of transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through a fiber optic cable, electrical signals communicated through a wire, and/or other transmission media. As will be understood by those of skill in the art, data is typically moved at some occasional points in time during normal operations of a storage device, such as during access, de-fragmentation or garbage collection, but this does not render the storage device as transitory because the data is not transitory while it is stored.
Referring to
COMPUTER 101 may take the form of a desktop computer, laptop computer, tablet computer, smart phone, smart watch or other wearable computer, mainframe computer, quantum computer or any other form of computer or mobile device now known or to be developed in the future that is capable of running a program, accessing a network or querying a database, such as remote database 130. As is well understood in the art of computer technology, and depending upon the technology, performance of a computer-implemented method may be distributed among multiple computers and/or between multiple locations. On the other hand, in this presentation of computing environment 100, detailed discussion is focused on a single computer, specifically computer 101, to keep the presentation as simple as possible. Computer 101 may be located in a cloud, even though it is not shown in a cloud in
PROCESSOR SET 110 includes one, or more, computer processors of any type now known or to be developed in the future. Processing circuitry 120 may be distributed over multiple packages, for example, multiple, coordinated integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and/or multiple processor cores. Cache 121 is memory that is located in the processor chip package(s) and is typically used for data or code that should be available for rapid access by the threads or cores running on processor set 110. Cache memories are typically organized into multiple levels depending upon relative proximity to the processing circuitry. Alternatively, some, or all, of the cache for the processor set may be located “off chip.” In some computing environments, processor set 110 may be designed for working with qubits and performing quantum computing.
Computer readable program instructions are typically loaded onto computer 101 to cause a series of operational steps to be performed by processor set 110 of computer 101 and thereby effect a computer-implemented method, such that the instructions thus executed will instantiate the methods specified in flowcharts and/or narrative descriptions of computer-implemented methods included in this document (collectively referred to as “the inventive methods”). These computer readable program instructions are stored in various types of computer readable storage media, such as cache 121 and the other storage media discussed below. The program instructions, and associated data, are accessed by processor set 110 to control and direct performance of the inventive methods. In computing environment 100, at least some of the instructions for performing the inventive methods may be stored in block 180 in persistent storage 113.
COMMUNICATION FABRIC 111 is the signal conduction path that allows the various components of computer 101 to communicate with each other. Typically, this fabric is made of switches and electrically conductive paths, such as the switches and electrically conductive paths that make up busses, bridges, physical input/output ports and the like. Other types of signal communication paths may be used, such as fiber optic communication paths and/or wireless communication paths.
VOLATILE MEMORY 112 is any type of volatile memory now known or to be developed in the future. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory 112 is characterized by random access, but this is not required unless affirmatively indicated. In computer 101, the volatile memory 112 is located in a single package and is internal to computer 101, but, alternatively or additionally, the volatile memory may be distributed over multiple packages and/or located externally with respect to computer 101.
PERSISTENT STORAGE 113 is any form of non-volatile storage for computers that is now known or to be developed in the future. The non-volatility of this storage means that the stored data is maintained regardless of whether power is being supplied to computer 101 and/or directly to persistent storage 113. Persistent storage 113 may be a read only memory (ROM), but typically at least a portion of the persistent storage allows writing of data, deletion of data and re-writing of data. Some familiar forms of persistent storage include magnetic disks and solid state storage devices. Operating system 122 may take several forms, such as various known proprietary operating systems or open source Portable Operating System Interface-type operating systems that employ a kernel. The code included in block 180 typically includes at least some of the computer code involved in performing the inventive methods.
PERIPHERAL DEVICE SET 114 includes the set of peripheral devices of computer 101. Data communication connections between the peripheral devices and the other components of computer 101 may be implemented in various ways, such as Bluetooth connections, Near-Field Communication (NFC) connections, connections made by cables (such as universal serial bus (USB) type cables), insertion-type connections (for example, secure digital (SD) card), connections made through local area communication networks and even connections made through wide area networks such as the internet. In various embodiments, UI device set 123 may include components such as a display screen, speaker, microphone, wearable devices (such as goggles and smart watches), keyboard, mouse, printer, touchpad, game controllers, and haptic devices. Storage 124 is external storage, such as an external hard drive, or insertable storage, such as an SD card. Storage 124 may be persistent and/or volatile. In some embodiments, storage 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 is required to have a large amount of storage (for example, where computer 101 locally stores and manages a large database) then this storage may be provided by peripheral storage devices designed for storing very large amounts of data, such as a storage area network (SAN) that is shared by multiple, geographically distributed computers. IoT sensor set 125 is made up of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another sensor may be a motion detector.
NETWORK MODULE 115 is the collection of computer software, hardware, and firmware that allows computer 101 to communicate with other computers through WAN 102. Network module 115 may include hardware, such as modems or Wi-Fi signal transceivers, software for packetizing and/or de-packetizing data for communication network transmission, and/or web browser software for communicating data over the internet. In some embodiments, network control functions and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (for example, embodiments that utilize software-defined networking (SDN)), the control functions and the forwarding functions of network module 115 are performed on physically separate devices, such that the control functions manage several different network hardware devices. Computer readable program instructions for performing the inventive methods can typically be downloaded to computer 101 from an external computer or external storage device through a network adapter card or network interface included in network module 115.
WAN 102 is any wide area network (for example, the internet) capable of communicating computer data over non-local distances by any technology for communicating computer data, now known or to be developed in the future. In some embodiments, the WAN 102 may be replaced and/or supplemented by local area networks (LANs) designed to communicate data between devices located in a local area, such as a Wi-Fi network. The WAN and/or LANs typically include computer hardware such as copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and edge servers.
END USER DEVICE (EUD) 103 is any computer system that is used and controlled by an end user (for example, a customer of an enterprise that operates computer 101), and may take any of the forms discussed above in connection with computer 101. EUD 103 typically receives helpful and useful data from the operations of computer 101. For example, in a hypothetical case where computer 101 is designed to provide a recommendation to an end user, this recommendation would typically be communicated from network module 115 of computer 101 through WAN 102 to EUD 103. In this way, EUD 103 can display, or otherwise present, the recommendation to an end user. In some embodiments, EUD 103 may be a client device, such as thin client, heavy client, mainframe computer, desktop computer and so on.
REMOTE SERVER 104 is any computer system that serves at least some data and/or functionality to computer 101. Remote server 104 may be controlled and used by the same entity that operates computer 101. Remote server 104 represents the machine(s) that collect and store helpful and useful data for use by other computers, such as computer 101. For example, in a hypothetical case where computer 101 is designed and programmed to provide a recommendation based on historical data, then this historical data may be provided to computer 101 from remote database 130 of remote server 104.
PUBLIC CLOUD 105 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and/or other computer capabilities, especially data storage (cloud storage) and computing power, without direct active management by the user. Cloud computing typically leverages sharing of resources to achieve coherence and economies of scale. The direct and active management of the computing resources of public cloud 105 is performed by the computer hardware and/or software of cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments that run on various computers making up the computers of host physical machine set 142, which is the universe of physical computers in and/or available to public cloud 105. The virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 143 and/or containers from container set 144. It is understood that these VCEs may be stored as images and may be transferred among and between the various physical machine hosts, either as images or after instantiation of the VCE. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCEs and manages active instantiations of VCE deployments. Gateway 140 is the collection of computer software, hardware, and firmware that allows public cloud 105 to communicate through WAN 102.
Some further explanation of virtualized computing environments (VCEs) will now be provided. VCEs can be stored as “images.” A new active instance of the VCE can be instantiated from the image. Two familiar types of VCEs are virtual machines and containers. A container is a VCE that uses operating-system-level virtualization. This refers to an operating system feature in which the kernel allows the existence of multiple isolated user-space instances, called containers. These isolated user-space instances typically behave as real computers from the point of view of programs running in them. A computer program running on an ordinary operating system can utilize all resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running inside a container can only use the contents of the container and devices assigned to the container, a feature which is known as containerization.
PRIVATE CLOUD 106 is similar to public cloud 105, except that the computing resources are only available for use by a single enterprise. While private cloud 106 is depicted as being in communication with WAN 102, in other embodiments a private cloud may be disconnected from the internet entirely and only accessible through a local/private network. A hybrid cloud is a composition of multiple clouds of different types (for example, private, community or public cloud types), often respectively implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technology that enables orchestration, management, and/or data/application portability between the multiple constituent clouds. In this embodiment, public cloud 105 and private cloud 106 are both part of a larger hybrid cloud.
The interconnect monitor structure 200 implements an interconnect wiring model that replicates a physical metal hardware (HW) interconnect wiring configuration of semiconductor chip designs. As shown, the interconnect monitor structure 200 is formed by a plurality of latch stages 2010-5 coupled together with minimal combinatorial logic in between, while various numbers of latch stages can be implemented with the interconnect monitor structure. The latch stages 2010-5 includes a plurality of latches 202 L0-L5, where each of the latches 202 is arranged to implement scannable stages to receive scan test pattern data, enabling flexibility for scan in and scan out test patterns of disclosed embodiments. Each of the latch stages 2010-5 includes a respective multiplexer structure 2041-5 to enable selectively bypassing one or more specific latch stages of selected latch chain positions. A respective long buffered wire segment 206 P1, 206 P2, 206 P3, 206 P4 coupled between latches L1 and L2, L2 and L3, L3 and L4, L4 and L5, via a respective one of the multiplexer structures 2041-4 enables efficient process monitoring of multiple variants of HW interconnect wiring configurations of semiconductor chip designs.
As shown, each of the respective scannable latches 202 L1-L5 of the latch stages 2011-5 is coupled to respective buffered wire segments 206 for receiving input scan test patterns and providing output scan test patterns. The scannable latch 202 L0 is an input setup latch that receives input scan test patterns coupled via multiplexer structure 204-5 to the latch stages 2011-5. Each multiplexer structure 2041-5 of the respective stages 2011-5 allows bypassing selected latches, i.e., based on pattern bypass settings (e.g., implemented with the Scan Test Pattern Control Module 184) to convert bypassed stage latches L0-L5 to transparent operation, i.e., allowing the scan test pattern output to follow the scan test pattern input. Each of the respective buffered wire segments 206 P1, P2, P3, and P4 represents a selected (i.e., variable) length within the replicated HW interconnect wiring configuration. Each of the respective buffered wire segments 206 P1, P2, P3, and P4 includes engineered wire configurations and stage placements to replicate one or multiple different HW interconnect wiring configurations for a specific chip design. The illustrated buffered wire segment 206 P4 includes a plurality of spaced apart inverters or drivers 208 that are provided to accurately replicate a specific segment of a given HW interconnect wiring configuration. For example, interconnect monitor structure 200 enables multiple variants of wire configurations and multiple different scan test patterns being applied on multiple wiring levels located in close proximity within the buffered wire segments 206 P1, P2, P3, P4. In an embodiment, different groups of bits are tagged as different wire configurations, (e.g., multiple wire code configurations 250 as illustrated in
Cm=B*N bits
In an embodiment, the wire codes for different wire configurations define interconnect wire and voltage parameters directly related to HW interconnect performance across a broad population of chip and wafer designs, including defined combinations of wire parameters, wire usage, and signal hostility for large-scale high-performance chip designs. The defined interconnect wire parameters include actual hardware interconnect wire size or width, spacing between wires, a wire layer, and an associated threshold voltage value, for multiple interconnect signal paths which directly affect interconnect RC parasitics to be determined. In the illustrated interconnect monitor structure 200, the long wire segments 206 P1 and 206 P2 of latch stages 201-2 and 201-3 can be effectively modeled by respective engineered wire configurations extending in a first direction from left to right, and the wire segments 206 P3 and 206 P4 of latch stages 201-4 and 201-5 are modeled extending in an opposite direction from right to left. Scan test patterns are generated based on intelligent pattern generation algorithms of Interconnect Process Monitor Control Code 182 and applied with the Scan Test Pattern Control Module 184 of disclosed embodiments, for example, including multiple different hostility scan test patterns directly affecting interconnect RC parasitics to be determined. The Interconnect Process Monitor Control Code 182 of the disclosed interconnect monitor structure 200 enables effective determination of RC parasitics between wires carrying signals that travel in both the same and opposite directions over long distances, closely modelling the actual combinations of wire usage and hostility that appear on a large-scale high-performance chip. The Scan Test Pattern Control Module 184 of the disclosed interconnect monitor structure 200 applies generated scan test patterns to one or more latch stages 201 across multiple wires of the interconnect monitor structure 200 to automatically determine interconnect RC parasitics of the one or more selected wire segments 206. In a disclosed embodiment, the generated scan test patterns can drive specific hostility signals on neighboring wires, and enable isolating hostility effects on the HW interconnect wiring configurations of various chip designs.
The interconnect monitor structure 200 enables efficient process monitoring to identify issues in multiple different layers of the replicated interconnect wiring configurations of the various chip designs. The interconnect monitor structure 200 enables isolating any of the stage latch stages 201-0, 201-1, 201-2, 201-3, 201-4. 201-5. The interconnect monitor structure 200 is selectively arranged in different chains of latch stages 2010-5, (e.g., implemented by Scan Test Pattern Control Module 184) to enable different stage distances (i.e., enabling a different device to wire parasitic ratio). The interconnect monitor structure 200 enables efficiently replicating different interconnect wiring configurations with scan in patterns directly applied to selected scan latches L0-L5, enabling efficient identification of metallization problems of multiple different interconnect layers, and validating wire RC paths across an entire chip path and across selected wire segments, such as selected wire segments, 206 P1, P2, P3, P4 (e.g., implemented by the Interconnect Process Monitor Control Code 182 and Scan Test Pattern Control Module 184).
Multiple operational modes of the interconnect monitor structure 200 are enabled based on the selected configuration of latch stages 2010-5, implemented by the Scan Test Pattern Control Module 184. For example, the impact of across chip variation (ACV) is minimized by running a bypass mode of the interconnect monitor structure 200, where intermediate latch stages, such as selected latch stages 201-2, 201-3, 201-4 and 201-5 are bypassed through the respective multiplexer structures 204. For example, a ring operational modes of the interconnect monitor structure 200 is implemented by feeding back an output of last latch stage 201-5 to the first stage 201-1 through the multiplexer structure 204-5. The ring operational mode of the interconnect monitor structure 200 enables efficient testing, providing effective test coverage to validate HW interconnect performance across a broad population of chip and wafer designs.
Operations begin at block 302 with a hostile or friendly base pattern, for example 011 or 010, where 010 represents a hostile base pattern, and 011 represents a friendly base pattern. In an embodiment, the friendly base pattern includes some repeating bit values, while the hostile base pattern includes alternating switching bit values. At block 304, the selected friendly or hostile pattern is expanded to fill an entire bit width. For example, an expanded hostile base pattern includes all switching bit values, such as 0101 0101 0101, for a 12-bit width.
In a given N bits per wire configuration, multiple different pattern hostility configurations are disclosed, such as, a scan test pattern of all bits switching provides a Hostile Hostile (HH) configuration, represented by:
Pattern 1: <0101 0101 0101>⇔<1010 1010 1010> Hostile-Hostile
Different variants of Hostile Quiet and Quiet Quiet configurations, (e.g., implemented by the computer 101 with the Interconnect Process Monitor Control Code 182 and the Scan Test Pattern Control Module 184), are provided by combining bits switching and rest or dead bits (i.e., held at logic 0 or 1), such as represented by:
Pattern 2: <0101 0001 0100>⇔<1000 1010 0010> Quiet-Hostile
Pattern 3: <0101 0101 0101>⇔<0000 0000 0000> Quiet-Quiet
Pattern 4: <0100 0001 0101>⇔<1010 1010 0010> Hostile-Hostile+Quiet−Quiet
For example, in the illustrated Patterns above, bit 1 (i.e., second bit from the left) is experiencing the listed hostility as it switches, except in Pattern 4, in which bit 1 sees Hostile-Hostile, while bit 4 sees Quiet-Quiet.
In a disclosed embodiment, providing different numbers of clock pulses with different pattern hostility, (e.g., implemented by the computer 101 with the Interconnect Process Monitor Control Code 182 and the Scan Test Pattern Control Module 184), enables isolation of any of the various latch stages 2010-5 of the interconnect monitor structure 200. In a disclosed embodiment, further providing different numbers of clock pulses along with bypass mode operation of the interconnect monitor structure 200 enables ACV testing.
Returning to
Referring to
In
At block 502, a scan order from a compiled model of a HW interconnect wiring configuration of a given chip design is consumed and a latch roster or list is created and translated from bank:stage:bit to latch chain or stage position of the interconnect monitor structure 200. At block 504, a linked network is constructed arranging bits, banks, and stages, for example, using python objects. At block 506, based on pattern bypass settings, (e.g., implemented by Scan Test Pattern Control Module 184) selected bypassed stage latches 202 L1-L5 are converted to transparent operation, and a pulse count of the pattern is determined to scan the pattern data through the linked network. At block 508, based on HH or FH base pattern, each latch is initialized with respect to 1.) Latch type, 2.) If it is removed from this pattern (Dead), 3.) Stage, and 4.) Inversion (where Inversion from scan-in pin taken into account). At block 510, using the updated linked network with the initialized latches and the pulse count determined at block 506, clock pulses are emulated by propagating scan initialized values through the linked network to calculate expected scan out values. At block 512, calculated initialization and expected result values for at speed testing use in the interconnect monitor structure 200 are prepared, including pulse count programming for the replicated HW interconnect wiring configurations implemented by the interconnect monitor structure 200, with clock speed programmed and scan out data obtained for at-speed trigger patterns.
At block 602, an interconnect monitor structure is provided, where the interconnect monitor structure comprises a plurality of latch stages, where each latch stage comprises a source latch, a buffered wire segment, and a capture latch. In a disclosed embodiment, scannable latches implement the plurality of latch stages and each latch stage includes a multiplexer structure, enabling multiple selected operational modes, such as a bypass operational mode of the interconnect monitor structure.
At block 604, the respective latch stages of the interconnect monitor structure are configured to define wire and threshold voltage configurations for each respective buffered wire segment of the plurality of latch stages to represent a hardware interconnect wiring configuration for a chip design. In a disclosed embodiment, engineered wire configurations for the respective buffered wire segments are defined by different wire configuration codes including groups of bits representing wire parameters or contributors impacting wire RC parasitics determined by the interconnect monitor structure 200. The wire configuration codes represent multiple wire parameters, such as wire width 254, space 256, layer 258, and threshold voltage VT 260 illustrated in
At block 606, one or more test scan patterns are scanned into the interconnect monitor structure 200 and output test scan patterns are captured from the interconnect monitor structure to determine wire Resistor-Capacitor (RC) parasitics of one or more buffered wire segments. The RC parasitics of one or more buffered wire segments reflect HW interconnect wiring characteristics of the hardware interconnect wiring configuration for the chip design. The test scan patterns represent different scan test hostility patterns directly affecting interconnect RC parasitics determined by the interconnect monitor structure. A number of functional clock cycles are determined for scanning in the test scan patterns into the interconnect monitor structure 200, to enable isolating selected latch stages. In an embodiment, one or more test scan patterns are scanned into the interconnect monitor structure with selected latch stages bypassed for monitoring ACV of the wire RC parasitics of the one or more buffered wire segments. At block 608, performance behavior of the hardware interconnect wiring configuration for the chip design is determined based on the RC parasitics of the one or more buffered wire segments.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
