Claims
- 1. A method of substantially simultaneously forming a substrate protection structure and a field effect transistor gate structure on a substrate wherein the substrate protection structure is used for protecting the substrate during a subsequent contact etch process and wherein the gate structure is included in a gate field effect transistor, comprising:
forming an etchable layer by,
depositing a gate oxide layer on the substrate; forming a first conductive layer on the gate oxide layer; depositing an dielectric cap layer over the first conductive layer; applying an etch mask on the dielectric cap layer, wherein the etch mask includes a filed effect transistor gate structure etch pattern that protects a first portion of the etchable layer suitable for forming the field effect transistor gate structure and wherein the etch mask further includes a substrate protection structure etch pattern that protects a second portion of the etchable layer suitable for forming the substrate protection structure; and substantially simultaneously forming the substrate protection structure and the field effect transistor gate structure by anisotropically etching, in a single etch process, those portions of the etchable layer that are not protected by either the field effect transistor gate structure etch pattern or the substrate protection structure etch pattern such that the substrate protection structure and the field effect transistor gate structure are formed of the same layers.
- 2. A method as recited in claim 1, wherein the gate oxide layer is a thermally grown layer of silicon dioxide.
- 3. A method as recited in claim 2, wherein the gate oxide layer is approximately 120 angstroms thick.
- 4. A method as recited in claim 3, wherein forming the first conductive layer comprises:
depositing a first polysilicon layer on the gate oxide layer; and depositing a silicide layer on the first polysilicon layer.
- 5. A method as recited in claim 4, wherein the first polysilicon layer is formed by a chemical vapor deposition process.
- 6. A method as recited in claim 5, wherein the first polysilicon layer is approximately 1500 angstroms thick.
- 7. A method as recited in claim 6, wherein the silicide layer is formed of tungsten silicide.
- 8. A method as recited in claim 7, wherein the tungsten silicide layer is approximately 2000 angstroms thick.
- 9. A method as recited in claim 8, wherein the dielectric cap layer is formed of silicon dioxide.
RELATED APPLICATIONS
[0001] This is a Continuation application of copending prior application Ser. No. 09/497,977 filed on Feb. 4, 2000, which is a continuation of prior application Ser. No. 08/837,529 filed on Apr. 21, 1997, which hereby takes priority therefrom.
Continuations (2)
|
Number |
Date |
Country |
Parent |
09497977 |
Feb 2000 |
US |
Child |
10005595 |
Nov 2001 |
US |
Parent |
08837529 |
Apr 1997 |
US |
Child |
09497977 |
Feb 2000 |
US |