BRIEF DESCRIPTION OF THE DRAWINGS
The drawings included herein provide a further understanding of the invention. A brief introduction of the drawings is as follows:
FIG. 1A is a schematic diagram of the multi-chip memory card of the prior art;
FIG. 1B is a schematic diagram of the circuit of the multi-chip system of the prior art;
FIG. 1C is a schematic diagram of the circuit of another multi-chip system of the prior art;
FIG. 1D is a schematic diagram of the low-resistance path caused by the multi-chip system that has a functional unit without a power supply of the prior art;
FIG. 2A is a signal waveform diagram of the output/input bus of the multi-chip system under normal conditions of the prior art;
FIG. 2B is a signal waveform diagram of the output/input bus of the multi-chip system that has a functional unit without a power supply of the prior art;
FIG. 2C is a signal waveform diagram of the output/input bus of the multi-chip system that has a functional unit without a power supply of the present invention;
FIG. 3A is a schematic diagram of the circuit of the multi-chip system of the preferred embodiment of the present invention;
FIG. 3B is a schematic diagram of the interface circuit of the common control unit and the functional unit of the first embodiment of the present invention; and
FIG. 3C is a schematic diagram of the interface circuit of the common control unit and the functional unit of the second embodiment of the present invention.