Patent Application
20090043928
1. Field of the Invention
The present invention generally relates to KVM switch systems, and more particularly to an interface device and a master device of a KVM switch system capable of processing the combined horizontal and vertical signals in an economical manner.
2. The Related Arts
KVM switch is widely popular in densely populated facility rooms as, instead of having dedicated keyboards, video displays, and mice, a single set of keyboard, video display, and mouse (therefore, the acronym KVM) is switched among and used to operate a large number of computers, thereby saving significant space and power, avoiding tangled wiring, and enhancing operational convenience.
For a conventional KVM switch, at least a cable is connected between the KVM switch and a computer for transmitting the video signal from the computer to the KVM switch for display on a video display connected to the KVM switch, and for transmitting the control signals from a keyboard and a mouse connected to the KVM switch to the computer for operating the computer. Then, by instructing the KVM switch to switch to another computer connected as such, the same video display can show the video output from the second computer and the same keyboard and mouse can be used to operate the second computer.
A recent development in the KVM switch is that twisted pair cables such as the Category 5 (CAT5) cables are used for the cabling between the KVM switch and the controlled computers as the CAT5 cables are able to provide signal transmission over an extended distance with high signal integrity. Usually, a small interface device is provided at a controlled computer and is connected to the keyboard, video, and mouse ports of the controlled computer. The interface device then converts the video signal to a format suitable for CAT5 cable and transmits the data to the KVM switch via a CAT5 cable, which decodes the data into the original video signal and sends the video signal to a connected video display. Similarly, the KVM switch encodes and sends the control signals from its connected keyboard and mouse to the interface device while the interface device decodes the data received from the KVM switch into original keyboard and mouse control signals and applies these control signals to the controlled computer.
U.S. Pat. No. 6,345,323 teaches a CAT5 KVM switch and the associated interface devices. In this teaching, the red, green, and blue video signals are transmitted over three twisted-pairs of the CAT5 cable, respectively. The horizontal and vertical sync signals are converted into positive going pulses and encoded onto two of the red, green, and blue video signals. The correct polarity of the horizontal and vertical sync signals is encoded onto the remaining one of the red, green, and blue video signals. In order to achieve conversion and encoding of the sync and polarity signals, sync combine and extract circuits are required in the interface devices. In some cases, the controlled computer provides a combined horizontal and vertical sync signal, instead of separate horizontal and vertical signals. To handle the combined horizontal and vertical sync signal, the sync combine and extract circuits would become quite complicated, thereby attributing a higher cost of the entire KVM switch system. In addition, these combine and extract circuits would introduce significant delay to the sync signals, which may cause shift and jitter in the displayed video. In the worst case, the video might not be properly displayed at all.
To overcome of the shortcomings of processing the combined horizontal and vertical sync signals in the prior arts, the present invention centralizes the processing the combined horizontal and vertical sync signals in a master device and thereby keeps the interface devices as simple as possible so as to reduce the cost of the interface devices.
According to the present invention, the interface device mainly only converts the separate horizontal sync signal and vertical sync signal, or the combined horizontal and vertical sync signal to a default polarity. On the other hand, the separation of the combined horizontal and vertical sync signal into individual horizontal and vertical sync signals are all carried out by the master device.
The foregoing and other objects, features, aspects and advantages of the present invention will become better understood from a careful reading of a detailed description provided herein below with appropriate reference to the accompanying drawings.
The following descriptions are exemplary embodiments only, and are not intended to limit the scope, applicability or configuration of the invention in any way. Rather, the following description provides a convenient illustration for implementing exemplary embodiments of the invention. Various changes to the described embodiments may be made in the function and arrangement of the elements described without departing from the scope of the invention as set forth in the appended claims.
According to the present invention, a number of interface devices 12 (shown in
The horizontal sync signal (H) and the vertical sync signal (V) are obtained from the video port of the computer 10 and fed to a pre-processing circuit 18, whose details are shown in
As shown in
However, there are cases that the horizontal sync lead of the video port provides a combined HV-sync signal while the vertical sync lead of the video port provides no signal. Therefore, a V-sync extraction unit 36 is provided to receive the output (i.e., in this case, a converted HV-sync signal) from the H-sync conversion circuit 28 so as to obtain the vertical sync signal. An additional OR logic 38 is therefore provided to receive the vertical sync signal either from the V-sync extraction unit 36 or from the V-sync conversion unit 30. The output of the OR logic 38 is then fed to the distance measurement unit 20 as the reference for synchronizing the 8 MHz signal. Please note that a major feature of the present invention is that the pre-processing circuit 18 does not provide any processing to the combined horizontal and vertical sync signal, which is fed to the differential driver unit 16 as it is. The complicated horizontal and vertical sync separation process is centralized and carried out by the mater device 40 altogether so as to simplify the interface device 12 and to reduce the cost of the interface device 12. Please also note that the synchronization to the 8 MHz signal is not required to be highly precise and, therefore, the V-sync extraction unit 26 can be implemented using simple resistor and capacitor (RC) circuit.
As shown in
The CPU 22 performs at least two tasks. One task is to transmit the original polarity (H pol) of the horizontal sync signal (H) and the original polarity (V pol) of the vertical sync signal (V) to the master device via an UART (Universal Asynchronous Receiver Transmitter) circuit 24 and the cable 14. The other task is to receive the keyboard and mouse control signals from the master device 40 via the cable 14 and the UART circuit 24, and apply the keyboard and mouse control signals to the keyboard and mouse connectors of the computer 10.
As shown in
Regardless whether the horizontal and vertical sync signals are combined or not, the extracted H′ and V′ signals are fed to a post-processing circuit 42 of the master device 40. As also mentioned earlier, the original polarities of the H′ and V′ signals are transmitted to the master device 40 via a CAT5 cable as well. Therefore, the post-processing circuit 42 restores the extracted H′ and V′ signals to have their original polarities by an H-sync polarity resume unit 50 and a V-sync polarity resume unit 52, respectively. The restored signals are then directly applied to the video port of a display device 60.
The master device 40 also contains an on-screen display (OSD) unit 58 for controlling the display device 60.
The post-processing circuit 42 contains a combined signal detection unit 46 which receives the H′ signal. If the combined signal detection unit 46 determines that the H′ signal is not the converted HV-sync signal, it will instruct a switching unit 62 of the post-processing circuit 42 to output the converted vertical sync signal (V′) to the OSD unit 58. On the other hand, if the combined signal detection unit 46 determines that the H′ signal is the converted HV-sync signal, it will instruct the switching unit 62 to output the converted vertical sync signal (V′) extracted from the converted HV-sync signal by a V-sync extraction unit 48. The converted vertical sync signal (V′) is also fed to a V-sync removal unit 54 and a glitch removal unit 56 of the post-processing unit 56 in parallel.
The V-sync removal unit 54 takes both the H′ signal and the output of the V-sync extraction unit 48 as inputs. If the H′ signal is the converted HV-sync signal, the V-sync removal unit 54 subtracts the converted vertical sync signal (V′) extracted by the V-sync extraction unit 48 from the converted HV-sync signal so as to obtain the converted H-sync signal. The converted H-sync signal is then put though the glitch removal unit 56 and then fed to the OSD unit 58. If the H′ signal is the converted H-sync signal, the V-sync extraction unit 48 obtains nothing and the V-sync removal unit 54 ends up sending the converted H-sync signal to the OSD unit 58 via the glitch removal unit 56.
As described above, the centralized processing of the separation of the combined HV-sync signal is able to provide more precise processing and more stable display to avoid flickering, drifting, etc. in the displayed video of the display device 60.
Although the present invention has been described with reference to the preferred embodiments, it will be understood that the invention is not limited to the details described thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.
