Patent Application
20160328306
The subject matter herein generally relates to an interface test device.
An interface should be coupled to a device which has an independent internet protocol address to get an identifiable signal.
Implementations of the present technology will now be described, by way of example only, with reference to the attached FIGURE.
The FIGURE is a block diagram of an embodiment of an interface test device.
Numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein.
Several definitions that apply throughout this disclosure will now be presented.
The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.
The FIGURE illustrates an embodiment of the interface test device 10. The interface test device 10 can comprise a first interface 101, a second interface 102, a test signal input interface 1017, a control signal input interface 1018, a power interface 1019, and a control module 110. The interface test device 10 is coupled between an electronic device and a computer 30. In the embodiment the electronic device is a motherboard 20.
The first interface 101 is coupled to a first test interface 201 of the motherboard 20. The second interface 102 is coupled to the second test interface 202 of the motherboard 20. The test signal input interface 1017 is coupled to a test signal interface 301 of the computer 30. The control signal input interface 1018 is coupled to a control signal interface 302 of the computer 30.
The power interface 1019 is coupled to an external power supply 40. The external power supply 40 supplies power for the interface test device 10. In other embodiments, the interface test device 10 can get power from an internal power module. The interface test device 10 can also couple to the computer 30 through the power interface 1019 to get power from the computer 30.
The control module 110 is coupled to the first interface 101, the second interface 102, the test signal input interface 1017, the control signal input interface 1018, and the power interface 1019. The computer 30 outputs different test signals to the test signal input interface 1017 through the test signal interface 301. The computer 30 outputs different control signals to the control signal input interface 1018 through the control signal interface 302. The control module 110 outputs different test signals selectively to the first interface 101 or the second interface 102, according to different control signals received.
To test the first test interface 201, the computer 30 outputs a first control signal through the control signal interface 302. The control module 110 receives the first control signal and outputs a first test signal to the first test interface 201.
To test the second test interface 202, the computer 30 outputs a second control signal through the control signal interface 302. The control module 110 receives the second control signal and outputs a second test signal to the second test interface 202.
In the embodiments, the interface test device 10 can comprise test interfaces 1016 which are coupled to the control module 110. The computer 30 outputs different control signals to the control module 110. The control module 110 outputs different test signals to a tested interface of the electronic device, according to the different control signals from the computer 30.
In the embodiment, the computer 30 can output a third control signal. The interface device 10 receives the third control signal, and outputs a third test signal to the first test interface 201 and the second test interface 202, to test both of the first test interface 201 and the second test interface 202 synchronously.
In the embodiment, the first interface 101, the second interface 102, the first test interface 201, the second test interface 202, and the test interfaces 1016 are RJ45 connectors. The control module 110 is a single chip microcomputer.
While the disclosure has been described by way of example and in terms of the embodiment, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201510234063.8 | May 2015 | CN | national |
