The disclosure relates to electrically-erasable programmable read only memory (EEPROM) devices, more particularly the disclosure relates to counting bit and/or byte failures in an EEPROM.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure claimed subject matter.
Throughout the following disclosure the term ‘NAND’ is used and is intended to refer to the logic function ‘not-AND’. The term ‘NAND flash’ is used throughout the disclosure and is intended to refer to a flash EEPROM device that employs tunnel injection for writing and tunnel release for erasing.
Particular embodiments described herein refer to NAND Flash EEPROM memory devices, however, in other embodiments the following disclosed device and method may be used in a variety of memory devices known to those of ordinary skill in the art and claimed subject matter is not so limited.
According to a particular embodiment, during programming, verification circuitry may evaluate bits in a byte and generate a failed byte signal if at least one bit of a byte has not been correctly programmed. According to a particular embodiment, circuit 100 may count the number of failing bytes, notifying a memory controller whether the number of failing bytes exceeds a tolerated amount of fails (K).
In a particular embodiment, a ‘failed bit’ or ‘failed byte’ is a bit or byte that may be programmed incorrectly and/or may not be programmed at all. In a particular embodiment, circuit 100 may comprise a sequence of failed byte counting assemblies; first FBCA 101, second FBCA 103 and nth FBCA 105. Such a sequence may comprise any appropriate number of FBCAs. In the following detailed description of
According to a particular embodiment, FBCA 101 may comprise, memory buffer 102 comprising 1−n data cache (DC) 104 and data detector (DDTC) 106. DCs 104 may comprise bytes of eight bits. In a particular embodiment, memory buffer 102 may be coupled to failed byte counting unit (FBCU) 108. DDTC 106 may comprise circuitry operable to determine whether bytes associated with an array page have been programmed properly. During a programming operation, DDTC 106 may check for failing bits in 1−n DC 104. If DDTC 106 detects a failed or improperly programmed bit, DDTC 106 may generate a “failed byte signal.” Thus, a failed byte signal, when asserted may indicate that at least one bit of a byte in any of 1−n DC 104 has been incorrectly programmed or not programmed at all.
In a particular embodiment, first FBCU 108 may be coupled to memory buffer 102. DDTC 106 may be capable of communicating to first FBCU 108 that there is at least one failed byte in memory buffer 102 in one or more of 1−n DC 104. According to a particular embodiment, first FBCU 108 may be coupled to additional Fail Byte Counting Units second FBCU 110 through nth FBCU 112. According to a particular embodiment, FBCU 110 and FBCU 112 may be coupled to respective memory buffers 107 and 109. FBCU 110 and FBCU 112 may also be capable of receiving failed byte signals.
According to a particular embodiment, a counting process may be enabled in a first FBCU 108 if a start signal 126 is asserted. Start signal 126 may also enable counter 124. In a particular embodiment, token 114 may be generated in response to start signal 126. FBCUs 108, 110 and 112 may be coupled via an enable signal chain 115 comprising enable signals 1−n, which may enable token 114 to cascade through FBCUs coupled via enable signal chain 115.
According to a particular embodiment, token 114 propagation and signal induction may be managed at least in part by State Machine (SM) 116 via control signals ‘ennext_ack’ 118 and ‘rising_ok’ 120. A particular embodiment of control signals ‘ennext_ack’ 118 and ‘rising_ok’ 120 signals are discussed in further detail with respect to
Referring still to
In a particular embodiment, counter 124 may count pulses generated in response to fail byte signals sent on out line out_fbc. Accordingly, circuit 100 may be able to count the total number of failing bytes determined in 1−n FBCA 101, 102 and 105.
According to a particular embodiment, circuit 100 may communicate a number of failing bytes calculated in counter 124 to a memory controller (not shown) or other processor running a programming algorithm that requests read/write data from a particular area of memory. Such a controller or processor may compare a number of failing bytes calculated by circuit 100 to a tolerated amount of fails for a particular function.
In a particular embodiment, in contrast to conventional methods, circuit 100 may enable counting of K failed bytes by waiting a time proportional to K, rather than scanning all of the n fail byte signals generated by all DCs in a page or sector selected for byte verification. For instance, in a particular embodiment, a threshold K of failed bytes may be predetermined. A sequence, which generates an out_fbc pulse for detection of a failed bit in a byte may take a number of clock cycles, Nclk. Accordingly, counting of a threshold number of failing bytes may take Nclk*K*Tclk where Tclk is the clock period with no delay.
In a particular embodiment, propagating a token though an FBCU where no failed byte signal is generated may delay propagation of a token by Tdel. In a particular embodiment, such delay may be on the order of 300 ps-500 ps. Thus, the time to count at least K failing bytes in a page comprising n bytes where there n-K DCs having no failed bytes may be equal to:
Tk=Nclk*K*Tclk+(n−K)*Tdel
In a particular embodiment, if FBCU 108 receives a fail byte signal, a pulse may be generated by token 114 and sent out on out_fbc line 208. However, if FBCU 108 receives a de-asserted fail byte signal or there is no fail byte signal then token 114 may be released without generating a pulse on out_fbc line 208. According to a particular embodiment, subsequent FBCU may receive token 114 via an enable chain.
In a particular embodiment, when there are no failed bytes in a page, failed byte signal 304 may be low. According to a particular embodiment, start signal 302 (or enable signal for subsequent FBCUS) may be asserted. According to a particular embodiment, not fail signal 318 may indicate that there are no failed bytes for a byte corresponding to FBCU 300. Accordingly, FBCU 300 may assert an enable out signal (en_out) 310 releasing a token (not shown) and enabling subsequent FBCUs. In a particular embodiment, SM 116 may act as a sequencer. When there are no failed bytes to count (such as when failed byte signal=L) SM 116 may not start sequencing and no output signal (out_fbc) 306 may be asserted.
In a particular embodiment, if there are failed bytes in a page to count. According to a particular embodiment, failed byte signal 304 may be high. According to a particular embodiment, start signal 302 may be asserted. After a rising edge of start signal 302 is detected, FBCU 300 may generate a negative edge by activating a pull down NMOS 312 on line out_fbc 306. According to a particular embodiment, SM 116 may sample a negative edge of signal out_fbc 306 as SM 116 is entering a Q1 state where SM 116 may activate an output signal rising_ok 314. Correspondingly, if FBCU 300 detects output signal rising_ok 314, FBCU 300 may deactivate NMOS 312, enabling signal out_fbc 306 to float. At this point, SM 116 may go into a Q2 state. After a clock cycle SM 116 may reach a Q2 state, where it may pull up out_fbc 306 line and reset a rising_ok 314 output signal.
In a particular embodiment, FBCU 300 may comprise NAND 324. An output of NAND 324 may be asserted if there is a failed bit in a byte corresponding to FBCU 300. In a particular embodiment, FBCU 300 may comprise NAND 326 which may generate a falling edge on out_fbc 306 line if an opportune state of FBCU 300 has been reached.
According to a particular embodiment, a negative pulse may be generated on out_fbc 306 line, enabling counter 124 (shown in
In a particular embodiment, a first FBCU in a sequence may start in a Q0 state 402. Q0 state 402 may be a state a first FBCU may be in prior to checking bits of a corresponding byte. According to a particular embodiment, en_out may be low, out_fbc may be floating if en_in is low and out_fbc may be low if en_in is high.
In a particular embodiment, when there are no failed bits in a corresponding byte, an FBCU may enter a Q1 state 404. According to a particular embodiment, going to Q1 state 404 a failed byte signal may be low, en_out may be high and out_fbc may be floating. According to a particular embodiment, an FBCU may be reset to a Q0 state 402 if reset signal goes high.
In a particular embodiment, when there are failed bytes to count in a corresponding byte an FBCU may enter a Q2 state 406. According to a particular embodiment, going to Q2 state 406 a failed byte signal may be high, rising_ok signal may be high, ennext_ack may be low and out_fbc may be floating. According to a particular embodiment, FBCU may be reset to a Q0 state 402 if reset signal goes high.
In a particular embodiment, when a failed bit of corresponding bytes has been counted an FBCU may enter a Q3 state 408 where an enable signal may be sent to a subsequent FBCU to initiate a fail bit counting process. According to a particular embodiment, going to Q3 state 408, a failed byte signal may be high, en_in signal may be high, ennext_ack may be high and out_fbc may be floating and a token may be released to the next FBCU in a sequence. According to a particular embodiment, FBCU may be reset to a Q0 state 402 if reset signal goes high.
In a particular embodiment, in Q1 state 504 a state machine may avoid activation of pull up pull down MOSFETs on the line out_fbc. In Q1 state 504, ennext_ack may be low, rising_ok may be high and out_fbc may be floating. In a particular embodiment, in Q1 state 504, SM 116 (see
In a particular embodiment, in Q2 state 508, SM 116 may pull up line out_fbc. In Q2 state 508, ennext_ack may be low, rising_ok may be low and out_fbc may be high. In a particular embodiment, in Q2 state 508 SM 116 may pull up line out_fbc. According to a particular embodiment, a fail may be counted at a rising edge of out_fbc or on a falling edge depending on clock polarity of a byte counter and claimed subject matter is not limited in this regard.
In a particular embodiment, for Q3 state 506, SM 116 may go into this state to acknowledge a release of a token to a subsequent FBCU 300 and assert a release signal ennext_ack. In Q3 state 506, ennext_ack may be high, rising_ok may be low and out_fbc may be floating.
In a particular embodiment, failing bits may be detected using data line 716 to read failed byte signals. According to a particular embodiment, during a fail bit counting operation control unit 704 may scan byte by byte over 1−n bytes 712 to count a number of failed bits. In a particular embodiment, control unit 704 may scan, for instance, during a test phase or during a self error detect phase and claimed subject matter is not limited in this regard.
In a particular embodiment, control unit 704 may be included in firmware of memory device 700. According to a particular embodiment, control unit 704 may manage a fail bit counting operation via internal firmware reducing reliance on an external testing unit.
In a particular embodiment, data line 716 may be used to access data to read and count a number of failed bits and or bytes. According to a particular embodiment, data to be read are on PDC 720, however data line 716 is coupled to SDC 720. In a particular embodiment, SDC 722 may be a latch of DDC 708 used to write data and read data into DDC 708. According to a particular embodiment, PDC 720 may be an internal latch of DDC 708 used to store (bit by bit) pass/fail information.
Data line 716 may be accessed to read pass/fail information from DDC 708 using SDC 722 as an access point by swapping data between SDC 722 and PDC 720. In a particular embodiment, pass/fail data on PDC 722 may be transferred to SDC 722 via bitline 780 and memory data on SDC 722 may be transferred to PDC 720 via bitline 780. Accordingly, reading failed byte signals from SDC 722 by swapping data from PDC 720 and SDC 722 via bitline 780 may enable use of data line 716 to read and count fail bit/byte data without incurring loss of SDC 722 data. However, this is merely an example of a method of swapping data between an SDC and PDC and claimed subject matter is not so limited.
In a particular embodiment, COMP 724 may be coupled to data detect circuit 726 and/or counter unit 730. According to a particular embodiment, COMP 724 may detect bit and/or byte fail conditions and may be enable one or more operations such as, for instance, a compare failed bit operation and a compare failed byte operation and claimed subject matter is not limited in this regard. According to a particular embodiment, a compare failed byte operation may enable detection of a byte fail without any reference to a specific bit location. In a particular embodiment, a compare failed bit operation may enable detection of specific bit within a byte.
In a particular embodiment, if no fail condition is detected, such a ‘no fail’ condition may be indicated, for instance, on a common line data verify of data detect circuit 726. A data verify line may be activated high and stay high when there is a ‘no fail’ condition. In a particular embodiment, if at least one fail condition is detected in comparison circuit 724 of enabled DDC 708, a common line data verify of data detect circuit 726 of a particular byte 712 (see
In a particular embodiment, after swapping data on PDC 720 and SDC 722, 1−n bytes 712 may be addressed. According to a particular embodiment, byte 712 may be evaluated and a detected fails may be counted by counter unit 730. In a particular embodiment, a number of fails over 1−n bytes 712 may be summed by adder unit 740. Summing may be done by adding a current fail to a previous one. Such an internal fail bit/byte counting operation may be performed in user mode during a program phase, by evaluating the result of a previous program verify and/or during a self error detect of a test phase. In a particular embodiment, during a test phase an internal fail bit/byte counting operation may enable determination of the number of fails in a 512 byte array sector.
Error correction coding may be able to correct a particular number of bit fails in a particular byte sector (for example, eight bit fails in a 512 byte sector). In conventional external fail bit/byte counting operations redundant bytes resulting from self error correction may be counted resulting in inaccurate fail bit/byte counts. For example, conventionally some failed bytes may be replaced by redundant columns, however, a specific redundant byte may not be correlated with a specific sector. For instance, redundant byte “0” may be used for byte 12 (first sector) or byte 700 (second sector). In this case, a conventional external fail bit/byte counter may inaccurately count bit fails in the first sector due to redundancy.
In a particular embodiment, an internal fail bit/byte counting operation may simplify fail bit/byte counting because when a failed bit/byte is addressed, internal fail bit/byte counter 700 evaluates fail bit/bytes from information originating on PDC 720 and may evaluate a redundant bit/byte wherever it is placed. For instance, when evaluating fails in a first sector, starting from address 0 up to address 511, if byte 12 fails, when byte 12 is addressed it may be the redundant byte that is evaluated. Therefore, a number of fails counted in a particular sector does not include an original fail bit/byte and a redundant bit/byte, only a redundant bit/byte may be evaluated. If byte 700 is a first failed byte, during counting of a first sector (from 0 to 511) redundant bytes in a second sector are not evaluated.
According to a particular embodiment, process 900 may flow to block 906 where an adder unit may be set to zero and a counter unit may be set to zero. In a particular embodiment, process 900 may flow to block 908 where a byte counting operation may occur. During such an operation bytes may be addressed via a data line coupled to a secondary data cache. According to a particular embodiment, failed bits and/or bytes may be detected by a comparison circuit.
According to a particular embodiment, process 900 may flow to block 910 where a counter unit may count failed bytes. In a particular embodiment, a failed bit and/or byte may generate a signal in a data detection circuit to detect fails. Detected fails in a particular block of data may be counted by a counter unit. Process 900 may flow to block 912 where total fails for a page may be summed in an adder unit and compared with a reference value (for example, max fail bits tolerated=20, if the number of fails=18 then ‘pass’ if the number of fails=25 then ‘fail’). Process 900 may flow to block 914 where data on PDC may be transferred back to SDC and data on SDC may be transferred back to PDC. Process 900 may end at block 916.
While certain features of claimed subject matter have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such embodiments and changes as fall within the spirit of claimed subject matter.