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GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/44Indication or identification of errors

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Techniques for retiring blocks of a memory system
- Patent number 12,362,030
- Issue date Jul 15, 2025
- Micron Technology, Inc.
- Deping He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device and method of testing the semiconductor device
- Patent number 12,354,690
- Issue date Jul 8, 2025
- SK hynix Inc.
- Jun Hyuk Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for memory chip row hammer threat backpressure...
- Patent number 12,347,507
- Issue date Jul 1, 2025
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Error detection pin encoding scheme to avoid maximum transitions an...
- Patent number 12,347,508
- Issue date Jul 1, 2025
- NVIDIA Corp.
- Sunil Sudhakaran
- G11 - INFORMATION STORAGE
Information Patent Grant
Interface read after write
- Patent number 12,346,603
- Issue date Jul 1, 2025
- Micron Technology, Inc.
- Yue Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device including flexible column repair circuit
- Patent number 12,334,173
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Hyungjin Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data integrity checks based on voltage distribution metrics
- Patent number 12,334,166
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Vamsi Pavan Rayaprolu
- G11 - INFORMATION STORAGE
Information Patent Grant
Operating and testing semiconductor devices
- Patent number 12,334,170
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Taewook Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link evaluation for a memory device
- Patent number 12,334,172
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Markus Balb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with error checking and correcting unit
- Patent number 12,327,600
- Issue date Jun 10, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Weibing Shang
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital verify failbit count (VFC) circuit
- Patent number 12,322,465
- Issue date Jun 3, 2025
- Yangtze Memory Technologies Co., Ltd.
- Teng Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Read cache memory
- Patent number 12,321,608
- Issue date Jun 3, 2025
- Micron Technology, Inc.
- Eugene Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory authentication
- Patent number 12,321,615
- Issue date Jun 3, 2025
- Rachael R. Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital verify failbit count (VFC) circuit
- Patent number 12,322,456
- Issue date Jun 3, 2025
- Yangtze Memory Technologies Co., Ltd.
- Teng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vehicle memory system based on 3D memory and method operating thereof
- Patent number 12,322,463
- Issue date Jun 3, 2025
- Hyundai Motor Company
- Hong Yeol Lim
- G11 - INFORMATION STORAGE
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Repairable semiconductor memory device
- Patent number 12,315,583
- Issue date May 27, 2025
- ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
- Min-Chung Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module register access
- Patent number 12,298,842
- Issue date May 13, 2025
- RAMBUS INC.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory repair system and method
- Patent number 12,300,337
- Issue date May 13, 2025
- QUALCOMM Incorporated
- Hong Dai
- G11 - INFORMATION STORAGE
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage devices and methods of operating storage devices
- Patent number 12,288,590
- Issue date Apr 29, 2025
- Samsung Electronics Co., Ltd.
- Eun Chu Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit retiring to mitigate bit errors
- Patent number 12,283,333
- Issue date Apr 22, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Technologies for repair of memory with access lines
- Patent number 12,277,985
- Issue date Apr 15, 2025
- Intel Corporation
- William K. Waller
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor devices
- Patent number 12,271,263
- Issue date Apr 8, 2025
- SK hynix Inc.
- Sang Sic Yoon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Content addressable memory and content addressable memory cell
- Patent number 12,266,412
- Issue date Apr 1, 2025
- Faraday Technology Corp.
- Yi-Hsin Tseng
- G11 - INFORMATION STORAGE
Information Patent Grant
3D stacked integrated circuits having functional blocks configured...
- Patent number 12,266,647
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus with circuit-locating mechanism
- Patent number 12,266,411
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Itamar Lavy
- G11 - INFORMATION STORAGE
Information Patent Grant
Technologies for dynamic accelerator selection
- Patent number 12,261,940
- Issue date Mar 25, 2025
- Intel Corporation
- Francesc Guim Bernat
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CRYPTOGRAPHIC KEY MANAGEMENT
- Publication number 20250232067
- Publication date Jul 17, 2025
- Micron Technology, Inc.
- Juane Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF OPERATING...
- Publication number 20250232828
- Publication date Jul 17, 2025
- Samsung Electronics Co., LTD
- Myeong-Woo Lee
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND APPARATUS
- Publication number 20250226048
- Publication date Jul 10, 2025
- Canon Kabushiki Kaisha
- KOICHI IWAO
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE
- Publication number 20250226051
- Publication date Jul 10, 2025
- Rambus Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE INCLUDING REPAIR MEMORY CELL AND REPAIR METHOD THEREOF
- Publication number 20250226047
- Publication date Jul 10, 2025
- Samsung Electronics Co., Ltd.
- TAEYUN KIM
- G11 - INFORMATION STORAGE
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20250225083
- Publication date Jul 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BUILT-IN SELF-TEST (MBIST) AND BIST ADAPTIVE PORT (BAP) FOR...
- Publication number 20250218527
- Publication date Jul 3, 2025
- Intel Corporation
- Rakesh Kandula
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS WITH CIRCUIT-LOCATING MECHANISM
- Publication number 20250201331
- Publication date Jun 19, 2025
- Micron Technology, Inc.
- Itamar Lavy
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
- Publication number 20250201330
- Publication date Jun 19, 2025
- SK HYNIX INC.
- Jeong Hwan SONG
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
- Publication number 20250190368
- Publication date Jun 12, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR DYNAMIC ACCELERATOR SELECTION
- Publication number 20250193295
- Publication date Jun 12, 2025
- Intel Corporation
- Francesc Guim Bernat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOOL FOR FAULT DETECTION AND CLASSIFICATION IN DESIGN AND GENERATIO...
- Publication number 20250174294
- Publication date May 29, 2025
- Arteris, Inc
- Xavier VAN RUYMBEKE
- G11 - INFORMATION STORAGE
Information Patent Application
INTERFACE READ AFTER WRITE
- Publication number 20250165191
- Publication date May 22, 2025
- Micron Technology, Inc.
- Yue Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEFECTIVE MEMORY UNIT SCREENING IN A MEMORY SYSTEM
- Publication number 20250157563
- Publication date May 15, 2025
- Micron Technology, Inc.
- Alex Frolikov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE DEVICE AND OPERATING METHOD THEREOF
- Publication number 20250157559
- Publication date May 15, 2025
- SK HYNIX INC.
- Jung Sik Choi
- G11 - INFORMATION STORAGE
Information Patent Application
NON-DESTRUCTIVE MEMORY SELF-TEST
- Publication number 20250157560
- Publication date May 15, 2025
- Siemens Industry Software Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR REPAIRING INPUT DATA DURING PROGRAM SUSPEND OPERA...
- Publication number 20250149106
- Publication date May 8, 2025
- SK HYNIX INC.
- Hee Joung PARK
- G11 - INFORMATION STORAGE
Information Patent Application
3D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED...
- Publication number 20250149531
- Publication date May 8, 2025
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORING MEMORY ARRAY OPERATIONAL INFORMATION IN NON-VOLATILE SUBARRAYS
- Publication number 20250130908
- Publication date Apr 24, 2025
- Micron Technology, Inc.
- Christopher John Kawamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logging a Memory Address Associated with Faulty Usage-Based Disturb...
- Publication number 20250131973
- Publication date Apr 24, 2025
- Micron Technology, Inc.
- Yang Lu
- G11 - INFORMATION STORAGE
Information Patent Application
EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS USING A LOOPBACK MODE...
- Publication number 20250131970
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Massimo Sutera
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR TRACKING WORD LINE ACCESSES
- Publication number 20250131972
- Publication date Apr 24, 2025
- Lodestar Licensing Group LLC
- Dong Pan
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND AN APPARATUS FOR DDR5 DIMM POWER FAIL MONITOR TO PREVENT...
- Publication number 20250124994
- Publication date Apr 17, 2025
- Intel Corporation
- Dat T. LE
- G11 - INFORMATION STORAGE
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METADATA STORAGE AT A MEMORY DEVICE
- Publication number 20250118388
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND MEMORY WITH CONFIGURABLE METADATA PORTION
- Publication number 20250111885
- Publication date Apr 3, 2025
- QUALCOMM Incorporated
- Jungwon Suh
- G11 - INFORMATION STORAGE
Information Patent Application
READ DESTRUCTIVE MEMORY WEAR LEVELING SYSTEM
- Publication number 20250104793
- Publication date Mar 27, 2025
- SEAGATE TECHNOLOGY LLC
- Jon D. TRANTHAM
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY AND OPERATION METHOD THEREOF
- Publication number 20250095769
- Publication date Mar 20, 2025
- SK HYNIX INC.
- Seung Chan KIM
- G11 - INFORMATION STORAGE

Indication or identification of errors

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Techniques for retiring blocks of a memory system

Semiconductor device and method of testing the semiconductor device

Method and apparatus for memory chip row hammer threat backpressure...

Error detection pin encoding scheme to avoid maximum transitions an...

Interface read after write

Memory device including flexible column repair circuit

Data integrity checks based on voltage distribution metrics

Operating and testing semiconductor devices

Link evaluation for a memory device

Memory with error checking and correcting unit

Methods and apparatus to facilitate atomic operations in victim cache

Digital verify failbit count (VFC) circuit

Read cache memory

Memory authentication

Digital verify failbit count (VFC) circuit

Vehicle memory system based on 3D memory and method operating thereof

Victim cache with write miss merging

Repairable semiconductor memory device

Memory module register access

Memory repair system and method

Write merging on stores with different privilege levels

Storage devices and methods of operating storage devices

Bit retiring to mitigate bit errors

Technologies for repair of memory with access lines

Semiconductor devices

Hybrid victim cache and write miss buffer with fence operation

Content addressable memory and content addressable memory cell

3D stacked integrated circuits having functional blocks configured...

Apparatus with circuit-locating mechanism

Technologies for dynamic accelerator selection

Patents Applicationslast 30 patents

CRYPTOGRAPHIC KEY MANAGEMENT

3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF OPERATING...

SEMICONDUCTOR DEVICE AND APPARATUS

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

MEMORY DEVICE INCLUDING REPAIR MEMORY CELL AND REPAIR METHOD THEREOF

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

MEMORY BUILT-IN SELF-TEST (MBIST) AND BIST ADAPTIVE PORT (BAP) FOR...

APPARATUS WITH CIRCUIT-LOCATING MECHANISM

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

TECHNOLOGIES FOR DYNAMIC ACCELERATOR SELECTION

TOOL FOR FAULT DETECTION AND CLASSIFICATION IN DESIGN AND GENERATIO...

INTERFACE READ AFTER WRITE

DEFECTIVE MEMORY UNIT SCREENING IN A MEMORY SYSTEM

STORAGE DEVICE AND OPERATING METHOD THEREOF

NON-DESTRUCTIVE MEMORY SELF-TEST

MEMORY DEVICE FOR REPAIRING INPUT DATA DURING PROGRAM SUSPEND OPERA...

3D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED...

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

STORING MEMORY ARRAY OPERATIONAL INFORMATION IN NON-VOLATILE SUBARRAYS

Logging a Memory Address Associated with Faulty Usage-Based Disturb...

EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS USING A LOOPBACK MODE...

APPARATUSES AND METHODS FOR TRACKING WORD LINE ACCESSES

METHOD AND AN APPARATUS FOR DDR5 DIMM POWER FAIL MONITOR TO PREVENT...

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

METADATA STORAGE AT A MEMORY DEVICE

SYSTEM AND MEMORY WITH CONFIGURABLE METADATA PORTION

READ DESTRUCTIVE MEMORY WEAR LEVELING SYSTEM

MEMORY AND OPERATION METHOD THEREOF