The present invention relates in general to integrated circuits and in particular to internal node offset voltage test circuits and methods.
Testing integrated circuits typically involves the evaluation of important parameters at various functional levels under differing operating conditions, such as temperature. For example, the overall operation of the chip may be tested in addition to the specific testing of particularly critical circuits or circuit blocks. This is especially important with respects to complex integrated circuits where the overall device functionality may fall within specifications but the functioning of one or more internal circuit blocks is nonetheless only marginal.
The actual implementation of an efficient test protocol for a given chip is a non-trivial task subject to many variables. Among other things, if on-chip test circuitry is to be used, that test circuitry must be non-invasive. In other words, the operation of the test circuitry should not in itself alter any of the critical operating parameters of the device or disturb a critical signal path. Additionally, depending on packaging limitations, it is not always practical to provide sufficient pins for observing all the internal circuits requiring test. Further, notwithstanding the problem of access, some means must be provided to trigger the internal circuitry test mode. Finally, but of no less importance, some decision must be made as to which parameters and nodes are to be tested.
Given the importance of testing at various functional levels of an integrated circuit, improved testing techniques are required. These techniques should be non-invasive, neither disturbing critical signal paths nor dictating undue changes in the physical configuration device or packaging. They should be flexibly amenable to the testing of various internal nodes on the integrated circuit in a cost- and time-efficient fashion.
The principles of the present invention are embodied in circuits and methods for verifying the operation of internal blocks of an integrated circuit across a range of operating conditions. In one embodiment, A method of testing an integrated circuit is disclosed including the step of setting a guardbanded limit for a parameter associated with an embedded node, a deviation from the guardbanded limit under a set of test conditions correlated with a failure of the integrated circuit across a range of operating conditions. A test is performed under the test conditions to detect deviations of the parameter from the guardbanded limit to detect failures of the integrated circuit over the range of operating conditions.
The principles of the present invention provide techniques for testing internal nodes in a non-invasive yet efficient manner. Specifically, a set of tests is described which allows borderline internal stages to be identified by observing offset voltages between differential stages and the effects such offset voltages have on the device's performance. One advantage of the set of tests is the elimination of the requirement that a large matrix of tests be performed to verify a varied number of operational conditions.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in
Amplifier 100 is based on a pair of differential-input, single-ended operational amplifiers 101a,b (A1 and A2) which will be described in further detail below. Each amplifier 101 receives at its non-inverting (+) input a corresponding one of the differential input signal pair VIn+ and VIn− and drives a corresponding differential output signal pair VOut+ and VOut−. A network of resistors 102a,c generates the feedback voltages to the amplifier 101 inverting (−) inputs.
In the preferred embodiment, each amplifier 101a,b is a multiple-stage device such as that shown in FIG. 2. In the illustrated embodiment, four differential integrator stages (I1, I2, I3, I4) 201a,d, coupled by summers 202a,b, form the low-frequency path. The exemplary weighted outputs from integrator stages 201 into summers 202 are shown in
In multiple-stage devices, an excessive output from one stage can overdrive one or more of the following stages in the signal path thereby deteriorating overall device performance. In the specific case of an operational amplifier with multiple internal amplifier stages, such as feedforward amplifiers 101a,b, an overly large offset at the output of a failed stage will overdrive the following stages. This will result in a measurable increase in noise and harmonic distortion at the outputs of amplifier 100. (In the preferred embodiment, summers 202 are designed such that the following integrator stages I3 and I4 will not saturate, even if one or more of the prior stages such as integrator stage I2 has failed, although the DC gain will be reduced. Stages such as I2 which are not preceded by a summer may however saturate when its inputs are overdriven, for example due to a failure of integrator stage I1.)
The problem of failing internal stages is compounded by the fact that “borderline” stages may operate properly under nominal operational conditions yet fail when those conditions change. For example, a given stage in the chain may produce a differential output within the maximum allowable voltage swing at nominal temperature but exceed that voltage swing with temperature change, resulting in the overdrive of the following stage.
With respects to operational amplifiers 101a,b, in order to obtain optimum performance all stages 201 should be operating in an active non-saturation state. As previously noted, in a multipath feedforward configuration the internal amplifier (integrator) stages are bypassed by a high frequency path. In order to insure large signal stability at start-up and during transients, the high frequency path prevails as the stronger path. During normal operation, the input offset of a given stage, for example integrator I4, is compensated for by the preceding low frequency path integrator, in this case integrator I3. The voltage drive required by stage I3 to compensate for the input offset voltage of following stage I4 is a function of the intervening summer 202. In particular, the output weight from integrator I3 into summer 202b is ½ and therefore integrator I3 must be capable of providing a minimum drive voltage at least twice as large as the input offset of integrator I4 in order to compensate. At the same time, the maximum input voltage swing ΔVMax, which a given stage, in this case I4 properly operates, is limited by the choice of transistor sizes and bias currents. Moreover, ΔVMax will also vary as a strong function of temperature and a weak function of the common mode and power supply voltages.
Consequently, to determine if the output stage of one integrator stage will overdrive the differential inputs of the following stage, a large matrix of temperature, common mode voltage, power supply voltage and similar factors would normally have to be tested. To do so however would be prohibitively expensive in time, monetary costs and added circuit complexity. The present inventive concepts on the other hand provide means by which a single measurement can be made for a particular temperature and performance predicted for the general case.
In a first test, the inputs VIn+ and VIn− to amplifier 100 are tied together. The measurement of ΔVX for each stage IX and each amplifier A1 and A2 for at single test temperature is then compared against a guardbanded-offset voltage ΔVXguard to determine if stage IX has failed.
Specifically, the guardbanded maximum value for ΔVXguard is statistically determined as strong functions of temperature and input transistor device size and weak functions of supply and common mode voltages. In other words, the guardbanded voltage ΔVXguard is the approximate maximum offset voltage that will not overdrive following integrator stage IX+1 under all operating conditions, taking into account the weighting through the intervening summer stages. For example, assume that the output voltage ΔVX1 from Stage X will just begin to saturate Stage X+1 under nominal test conditions (e.g. temperature, bias current, common mode voltage, process variation) while an output voltage ΔVX2 will saturate Stage X+1 under a second statistically or experimentally determined set of conditions. Then the guardbanded voltage ΔVXguard is selected to be within the window of ΔVX2 such that when a single measurement is made under nominal test conditions, potential failures under the second set of conditions are also detected. This is illustrated graphically in
This test feature can be supplemented by a window comparator or similar error detection circuit 600 monitoring each voltage ΔVx. An exemplary differential window comparator is shown in FIG. 6A and the corresponding test limits in FIG. 6B. In this case, a single pass/fail flag can be switched to the analog test output pins through multiplexers.
Another test technique according to the inventive principles is illustrated in FIG. 7. Again amplifier 100 inputs VIn+ and VIn− are tied together. Here, however, the tail current to each of the integrator stages 201 is stepped down under digital control. In
Another embodiment of the present principles is illustrated in
In sum, the present concepts advantageously provide circuits and methods for efficiently testing internal stages of an integrated circuit. In particular, these circuits and methods provide for the testing of offset voltages at selected points within a device, such as between integrator stages in a feedforward multiple-integrator differential amplifier. From these offset voltages and changes thereto, failed states whose outputs will overdrive the following stages under selected test conditions can be detected. Moreover, these offset voltages can be tested without having to resort to a large matrix of temperature, common mode voltage and power supply voltage test conditions.
Although the invention has been described with reference to specific embodiments, these descriptions are not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed might be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
It is therefore, contemplated that the claims will cover any such modifications or embodiments that fall within the true scope of the invention.
Number | Name | Date | Kind |
---|---|---|---|
5184162 | Saitoh et al. | Feb 1993 | A |
5861774 | Blumenthal | Jan 1999 | A |
6483338 | Weng et al. | Nov 2002 | B1 |
6504394 | Ohlhoff | Jan 2003 | B1 |