The present invention relates to system-on-a-chip (SoC) design, and more specifically, to an intra-run design decision process for circuit synthesis.
In SoC design, a register-transfer level (RTL) design is implemented in a physical design based on processes that include high-level synthesis, logic synthesis, and physical synthesis. As part of one or more of the synthesis processes, different synthesis scenarios may be tried by modifying synthesis parameters (e.g., switch settings). A given synthesis run typically includes several stages. Parameters are often enacted at different stages of a synthesis run. Thus, parallel scenarios are possible at certain stages to consider different parameters, and parallel processing may be used to implement parallel runs. While an exhaustive trial of every scenario (every combination of parameters) may result in the most efficient physical design, each synthesis run represents a drain on available computational resources and disk space.
According to one embodiment of the present invention, a method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design includes executing, using a processor, a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters; determining, using the processor, a quality measure associated with each of the two or more scenarios; and performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.
According to another embodiment, a system to perform an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design includes a memory device configured to store instructions and information; and a processor configured to execute the instructions to execute a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, determine a quality measure associated with each of the two or more scenarios, and perform the intra-run decision to eliminate one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.
According to yet another embodiment, a computer program product performs intra-run decision making during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design. The computer program product comprises a computer readable storage medium having program code embodied therewith, the program code executable by a processor to perform a method including executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters; determining a quality measure associated with each of the two or more scenarios; and performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
As noted above, synthesis is a part of SoC design that facilitates translation of the logic design to a physical implementation. Different parameters representing different scenarios may be tried in different runs of the synthesis process to determine the desired physical implementation. However, as also noted above, trying too many scenarios can tax the computational and disk space resources of the design system. Previously, two techniques were generally discussed as ways to cut resource usage in synthesis runs. These techniques include checkpointing and forking. Embodiments of the systems and methods detailed herein relate to pruning and combining pruning with checkpointing and forking in order to increase the number of scenarios considered in the synthesis while reducing resource usage. The embodiments discussed herein with reference to synthesis may apply to high-level, logic, and physical synthesis generally. The change or improvement in synthesis results for different sets of parameters (scenarios) may be judged based on differences in quality of results (QOR) associated with the different scenarios. The QOR for each run may be determined in terms of timing, power consumption, and congestion. As used below, fork, forking, and fanout all refer to generating scenarios by combining parameter values or parameter combinations from one stage with two or more parameter values or parameter combinations in a subsequent stage.
At stage 2210-2, three fanouts or forks (F2=3) are used to test three different parameter values or combinations of parameters (h2, i2, j2) with each of the surviving scenarios (b1, f1) from stage 1210-1. As a result, the number of scenarios in stage 2210-2 is 6 (N2=6). That is, the number of scenarios considered at a given stage is determined by the number of surviving scenarios (S) of the previous stage and the number of parameter values or parameter combinations to be tried at the given stage, which is represented by the number of forks or fanouts (F) at the given stage:
Ni+1=Si×Fi+1 [EQ. 1]
At the end of stage 2210-2, another evaluation 220-2 is performed. As noted above, the evaluation 220-2 may be based on QOR associated with each of the six scenarios run in stage 2210-2 and may look for the highest two QOR values (or some other number of highest QOR values) or may select to continue all scenarios whose associated QOR exceeds a threshold. All other scenarios are pruned. According to this procedure, in the example shown in
Rules may be established to account for the fact that some parameters or parameter combinations (scenarios) may not improve QOR immediately but may prove advantageous in a later stage. These rules may be established based on a baseline or previously archived results. The baseline scenario is further discussed below. As an example of one of these rules, a surviving scenario from one stage may be flagged to be continued to the end, even if scenarios stemming from that surviving scenario do not survive in subsequent stage. For example, in the example discussed with reference to
As noted above, evaluation 220 after each stage may be performed based on a comparison of QOR resulting from each scenario. Some number of scenarios associated with the top QOR values may be retained or all scenarios associated with QOR values that exceed a threshold may be retained (all scenarios associated with QOR values below the threshold may be pruned). According to an exemplary embodiment, a baseline scenario may be run. This baseline scenario may be run live (in conjunction with test scenarios) or may be pre-run such that the results are archived. The baseline run may represent a metric by which other scenarios are judged. That is, rather than a pre-defined threshold QOR, the baseline scenario QOR at a given stage may be used to evaluate scenarios. The baseline run, whose resource cost is known, may be used to determine how much pruning to do at a given stage to maintain a specified level of resource usage. Every scenario run may be recorded in a report for comparison with the baseline. Some scenarios may be blacklisted in the interest of resource usage. For example, the highlighted combination (scenario) consisting of b1, j2, m3 may be blacklisted (pruned despite evaluation results that indicate that the scenario should be continued to subsequent stages). The blacklisting may be based on several factors. For example, that particular combination or scenario may be part of the baseline such that its results are already known and the other scenarios are run as a comparison. As another example, the combination may be known to be undesirable based on archived data of test runs.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated
The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Number | Name | Date | Kind |
---|---|---|---|
5841663 | Sharma et al. | Nov 1998 | A |
6308313 | Lakshminarayana | Oct 2001 | B1 |
6345378 | Joly et al. | Feb 2002 | B1 |
6785875 | Beerel et al. | Aug 2004 | B2 |
7500216 | Blunno et al. | Mar 2009 | B1 |
8082138 | Bakshi et al. | Dec 2011 | B1 |
9529951 | Gristede | Dec 2016 | B2 |
20050062496 | Gidon | Mar 2005 | A1 |
20100031206 | Wu | Feb 2010 | A1 |
20100318492 | Utsugi | Dec 2010 | A1 |
20120036138 | Carrion | Feb 2012 | A1 |
20120226890 | Yoshida | Sep 2012 | A1 |
20130305198 | Yamamoto | Nov 2013 | A1 |
20150347641 | Gristede | Dec 2015 | A1 |
20160147932 | Liu | May 2016 | A1 |
Number | Date | Country |
---|---|---|
0806736 | Nov 1997 | EP |
Entry |
---|
List of IBM Patents or Patent Applications Treated as Related; (Appendix P), Filed Aug. 27, 2015; 2 pages. |
Christopher J. Berry et al., “Intra-Run Design Decision Process for Circuit Synthesis”, U.S. Appl. No. 14/837,102, filed Aug. 27, 2015. |
Myers et al., “Automatic Synthesis of Gate-Level Timed Circuits with Choice”, IEEE, 1995, 1-17. |
List of IBM Patents or Patent Applications Treated as Related; (Appendix P), Filed Jun. 30, 2015; 2 pages. |
George Diedrich Gristede et al., “Synthesis Tuning System for VLSI Design Optimization”, U.S Appl. No. 14/290,886, filed May 29, 2014. |
List of IBM Patents or Patent Applications Treated as Related; (Appendix P), Filed Dec. 15, 2016; 2 pages. |
George Diedrich Gristede et al., “Synthesis Tuning System for VLSI Design Optimization”, U.S. Appl. No. 15/358,615, filed Nov. 22, 2016. |
Number | Date | Country | |
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20170004243 A1 | Jan 2017 | US |