The present invention relates generally to photovoltaic cells and the detailed layer structure thereof. More specifically, the present invention relates to the structure of a thin-film PV cell that is intrinsically semitransparent and the method of making such a device including control of the transmitted light color or spectrum and control of the reflected light color or spectrum.
The vast majority of photovoltaic devices or solar cells are fully opaque so that essentially all light incident on the cell is absorbed by the cell or module. Maximizing the light absorption will maximize the power generated by the solar cell. However, in some applications it is desired to use the PV device in an arrangement that allows some of the light to pass through the device, such as in a window, skylight, or canopy. There are a number of module structures in which some light transmission has been obtained by spacing the cells such that light passes between individual cells in a module (e.g., wafer silicon modules) There are other structures that use thin-film PV in which some of the PV coating has been removed, such as by laser scribing or chemical etching. These solutions have the significant disadvantage of yielding a spatially non-uniform light transmission which is often undesirable.
There are some other thin-film PV materials that offer partial light transmission without such spacing of cells or selective removal. These are organic PV (small molecule or polymer) and dye sensitized solar cells (DSSC) which have relatively narrow absorption bands that absorb strongly in some spectral regions and weakly in others. This yields light transmission that is highly colored and also poor PV efficiency because only a narrow band of the visible spectrum is absorbed.
The present invention relates generally to PV cells and methods of fabrication thereof. More particularly, this invention relates to a PV cell having an absorber layer sufficiently thin but uniform and pinhole free so as to be semitransparent but still to have high efficiency as a solar cell or module. This invention also identifies a suitable transparent back contact that functions well with the preferred embodiment. Finally, the present invention also discloses the method of manufacturing such a semitransparent PV device.
a is an SEM micrograph cross section of CdTe sputter deposited under conditions suitable for ultra-thin PV.
b is an SEM micrograph cross section of CdTe sputter deposited under conditions unsuitable for ultra-thin PV.
a is a partial side view of a monolithic interconnect scheme using laser scribing to minimize the dead area and maintain clean visual appearance.
b is a partial side view of a monolithic interconnect scheme using laser scribing with insulating ink backfill of the P1 scribe.
a is a cross sectional view of a back contact layer of the present invention.
b is a cross sectional view of another feature of a back contact layer.
The present invention utilizes an inorganic semiconductor, such as CdTe, that has a very broad absorption spectrum, e.g., spanning the entire visible spectrum. In the present invention the transparency is accomplished by thinning the semiconductor layers sufficiently to achieve partial transparency and using specially developed structures for the front and back electrodes that are also transparent. This is the first time such a structure with high efficiency has been developed successfully using inorganic materials. The fabrication methods of such a structure are identified here. The features of the invention will be more readily understood by reference to the attached drawings in connection with the following description.
In order to make a solar cell that inherently transmits some of the light incident on it while utilizing most of the light to generate current and voltage in the solar cell, it is necessary to fabricate extremely thin layers that have a thickness of the order of the absorption length (1/absorption coefficient). For the case of cadmium telluride (CdTe) this requires a thickness of about 100 nm to about 750 nm with a thickness from about 250 nm to about 500 nm being preferred. In addition, alloys of CdTe, such as CdZnTe can also be used in this invention. For the case of cadmium sulfide (CdS) the thickness of this layer would be from about 30 nm to about 120 nm. Such thin layers that are also free of pinholes are difficult to fabricate by most methods. For example, close spaced sublimation (CSS) and vapor transport deposition (VTD), commonly used for CdTe layer deposition, exhibit large densities of small void spaces or pinholes so that when the thickness is less than about 1500 nm, these non-uniformities cause severe shunting of the solar cell which becomes increasingly severe for thin layers. These shunting problems are aggravated as the area increases toward large PV modules with size of 1 square meter or larger. Thus it is critically important to be able to deposit the semiconductor layers with extremely low density of pinholes and other non-uniformities. In the present invention, we show how this can be done by choosing carefully the magnetron sputter deposition parameters.
Another critically important issue for achieving transparent thin-film PV structures is that all other layers of the cell or module must also be transparent. This includes a transparent conductor or transparent conducting oxide (TCO) used in most cells and modules. It also includes a high resistivity transparent (HRT) layer also used in many thin-film cells and modules. The HRT layer can be positioned between the TCO and semiconductors. An HRT or other buffers can also be positioned between the semiconductors and the back contact or back conductive electrode layer (BC). The HRT or buffer layers can be used to reduce the effects of any pinholes or weak diodes on the performance of the solar cell. The HRT or buffer layers can also be used to adjust the energy band alignments to facilitate electron and hole transport across the interface between layers of the solar cell. But significantly, it also includes a transparent back contact on the far side of the cell or module that is spaced farthest from the sun. Here we identify materials and fabrication processes needed for such a transparent back contact (BC) for the preferred embodiment, the semitransparent CdS/CdTe solar cell and module.
Referring now to the drawings,
In order to obtain a high performance solar cell/module with ultra-thin absorber layers, it is necessary to deposit a very dense film that is essentially free of pinholes or voids. This presents a serious limitation to conventional deposition methods such as vapor transport deposition and close spaced sublimation or vacuum evaporation. Magnetron sputter deposition when performed under suitable conditions can provide such high quality, dense films. An example is presented in
The sputter deposition process can be optimized to provide deposition conditions that are especially well suited to depositing very uniform coatings on moderately curved surfaces, such as surfaces for auto sunroofs. This is explained below.
Earlier work by Compaan, et al. demonstrate/claim that magnetron sputtering, when performed under suitable conditions (gas pressure, rf or dc power, substrate heating) permits high performance coatings suitable for high efficiency thin film solar cells with the substrate held at relatively low temperatures. For example, sputtering can be done at ˜250° C. compared with temperatures for thermal evaporation, closed space sublimation, or vapor transport deposition which are 550° C. to 600° C. In practice it has been found that the sputtering process can be conducted from about 150° C. to about 350° C. with the preferred application being less than 250° C. Lower temperature deposition is possible because of the additional kinetic energy coming to the growth surface from the energetic atoms and ions during sputtering. This has the effect of increasing the surface adatom mobility over that which occurs with thermal activation alone, that is, without the sputter plasma assist. The extra kinetic energy of the incoming atoms (either the argon sputter gas atoms or the sputtered atoms such as Cd, Te, or S) helps to enhance the mobility of atoms on the growth interface so that the atoms find the lowest energy locations which are usually the best crystallographic positions.
The sputter gas pressure is important in determining how many collisions an atom sputtered from the target will undergo before reaching the growth interface. For RF sputtering the sputtered atoms have initial kinetic energies from a few electron volts (eV) to some tens of eV. Removing some of this initial kinetic energy through collisions is important to avoid damage to the growing semiconductor film. The mean free path (mfp) between collisions is given by kinetic theory which shows that for a gas temperature of 100° C. and argon gas pressure of 10 milliTorr (mTorr), the mfp is about 2 cm. We find that the optimum pressure for sputtering the ultra-thin layers of CdTe is in the range where there are approximately 1 to 3 collisions before reaching the film growth interface. For a substrate 10 cm from the sputter target, a pressure of 5 mTorr gives about 2-3 collisions when the gas kinetic temperature is about 100° C. (Larger target-to-substrate distances would require lower gas pressure for optimum film growth, and vice versa.) Higher pressures reduce the sputtered atom kinetic energy too much, scatter atoms away from the substrate and lower the deposition rate. Lower pressures produce too much ion bombardment of the growing film which is undesirable for CdTe and related absorber materials. For the materials of the semiconductor junction, especially CdTe, we require the lowest possible defect density and void density. These are best obtained with Ar sputter gas pressure in the range of 3-50 mTorr and preferably in the range of 5-15 mTorr. Ar gas purity is important and best results are obtained with 99.999% pure argon.
If the kinetic energy of the atoms at the growth surface is only due to the temperature of the substrate, then the best film properties are usually obtained at the highest possible temperatures where the adatoms have their highest mobility. This typically is limited by the softening point of the glass or to about 600° C. for soda-lime glass. Even higher temperatures have been used with borosilicate glass and other glass formulations with higher melting points. This is part of the reason that most record efficiency CdS/CdTe cells have used these special glass compositions.
When growth is performed at high temperatures, the film growth rate is a delicate balance between the incoming growth flux from the source and the reverse sublimation rate from the film. The sublimation rate from the film is exponentially sensitive to the inverse of the substrate temperature:
Sublimation rate=constant×T1/2exp(−Ea/kT), where Ea is the activation energy for sublimation.
Consequently, small variations in temperature, which are highly likely with curved substrates, will produce large changes in sublimation rate and consequently large variations in the net growth rate. Since sputter growth can be done at much lower substrate temperatures, this variation in sublimation rate across a substrate due to small variations in substrate temperature is much less of a problem. The consequence is that sputter deposition facilitates more uniform films across the entire substrate even with curved substrates and with some variation in temperature.
Traditional thin-film PV, including CdTe-based modules, are not very sensitive to variations in the film thickness, since the cell performance is only weakly dependent on the CdS or CdTe thicknesses. However with semitransparent, ultra-thin CdTe modules, the light transmission is very sensitive to the thickness of the CdTe in the range below 750 nm where significant light transmission occurs. Therefore, it is very important for transparent PV applications to be able to control the layer thickness with extreme accuracy.
We claim that magnetron sputter deposition provides the required control of thickness that can yield very uniform films even over curved surfaces. The control is sufficient to avoid noticeable variations on light transmission through different regions of a curved glass piece such as an auto sunroof.
It should be recognized that the deposition process must achieve appropriate doping levels in the semiconductors, excellent composition control, high quality grain structure, and good grain boundary passivation in order to yield high efficiency devices. These requirements are met by sputtering under appropriate conditions as described previously.
The performance of small CdS/CdTe solar cells over a range of absorber thicknesses is shown in
Referring to
In a preferred embodiment of the invention, the transparent electrode layer 14 is any one or more of the group zinc oxide (ZnO), zinc sulfide (ZnS), cadmium oxide (CdO), tin oxide doped with fluorine (SnO2:F), indium oxide doped with tin (In2O3:Sn), gallium oxide (Ga2O3), combinations of the preceding and other well known compositions transparent conductive coatings comprised of metal dielectric layers. Most preferably, the transparent electrode layer 14 is ZnO. Also, preferably, the transparent electrode layer 14, whether ZnO, ZnS or CdO, and is doped with a Group III element to form an n-type semiconducting layer. Most preferably, the transparent electrode layer 14 is ZnO doped with aluminum or SnO doped with fluorine. Layer 18 is a high resistivity transparent (HRT) layer which may be any one of the group specified for layer 14 but without doping so that the electrical resistance is high. Preferably this HRT layer is ZnO or SnO2 with thickness of about 25 nm to about 200 nm; most preferably with a thickness from about 50 nm to about 100 nm.
The first of two primary semiconductor layers, together forming an active semiconductor junction 30, is an n-type semiconductor layer 20. In a preferred embodiment of the invention this n-type semiconductor layer 20 is cadmium sulfide (CdS). The second primary semiconductor layer is a p-type semiconductor 22, which is preferably cadmium telluride (CdTe) or an alloy of CdTe. Numerous other semiconductor layers can be used for either of these two primary semiconductor layers, as will be appreciated by those skilled in the art. It is to be understood that an intrinsic semiconductor layer, not shown, can be disposed between the n-type semiconductor layer and the p-type semiconductor layer in conjunction with the present invention.
An optional layer of back buffer material is indicated at 24. Typically, this layer may be CdTe heavily doped with copper or a layer of tellurium formed by chemical etching of CdTe or a layer of ZnTe doped with Cu or ZnTe doped Cu with N. The back buffer layer 24 acts to provide an interface between the p-type semiconductor layer 22 and a back conductive electrode layer 26, which is the second of the two ohmic contacts or electrodes for the photovoltaic cell 10. The conductive back electrode layer 26 contains a conductive lead 28 for conducting current through the electric circuit, not shown. Typically, the conductive electrode layer is made of nickel, titanium, chromium, aluminum, gold or some other conductive material. Optionally, an additional protective or buffer layer 24 of zinc telluride, not shown, can be positioned between the back contact layer 26 and the cadmium telluride semiconductor layer 22 to facilitate hole (positive charge carrier) transport from the cadmium telluride layer to the back electrode layer and to protect the cadmium telluride layer form foreign contamination by migration. Also, it is to be understood that the layer 24 of back buffer material and the back electrode layer 26 can sometimes be combined into a single layer, not shown. To handle both functions in a single contacting layer, the single layer would have to have an electrical conductivity substantially equivalent to that of the back electrode layer 26, and yet still would have to be capable of making good transition to the CdTe semiconductor layer.
The photovoltaic cell 10 includes a substrate layer 12, which preferably is a glass substrate 12. Other transparent materials, such as polyimides, can be used for the glass substrate 12. A layer of a transparent conductive material, such as a transparent electrode layer 14, is applied to the glass layer 12. The transparent electrode layer 14 forms one of the two ohmic contacts or electrodes for the photovoltaic cell 10, and contains a conductive lead 16 for conducting current through an electric circuit, not shown. The transparent electrode layers are also sometimes referred to as a transparent conductive oxide, although some useful materials for this purpose are not oxides.
This back contact (BC) 26 must have suitable electronic characteristics as required for a back contact to CdTe and it must be transparent. Among the required electronic properties are that the work function must be a good match to the electron affinity of the CdTe layer 22 such that the positive charge carriers (holes) can flow readily into the BC. The embodiment of BC preferred in the prototype window unit that is shown in
The embodiment of BC preferred in
Monolithic integration is an important part of fabricating a large-area module 32 that is suitable for window applications 30. The illustration of
As shown in
The potential performance for such semitransparent modules when implemented in buildings is shown in
Additional features of the preferred embodiment include a process step involving activation with heat treatments of vapors of CdCl2. It may also include a suitable process for shunt passivation and the blocking of occasional pinholes using well-known steps of negative photoresists or other processes. This passivation step is preferably done after the activation step and before the application of the back contact. It may also involve the incorporation of a high resistance buffer layer between the CdTe and the BC.
For use as a window PV generation device, it may be desired to include an integral micro-inverter on each window or module to provide AC power out from the PV window that is suitable for integration into the home or business electrical system, typically 110 V or 220 V for the U.S. This AC power output can facilitate a “plug-and-play” installation in buildings.
The above detailed description of the present invention is given for explanatory purposes. It will be apparent to those skilled in the art that numerous changes and modifications can be made without departing from the scope of the invention. Accordingly, the whole of the foregoing description is to be construed in an illustrative and not a limitative sense, the scope of the invention being defined solely by the appended claims.
This application claims the benefit of U.S. Provisional patent application Ser. No. 61/465,155 filed Mar. 15, 2011.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/US12/29214 | 3/15/2012 | WO | 00 | 9/10/2013 |
Number | Date | Country | |
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61465155 | Mar 2011 | US |