Inverter circuit

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention This invention relates to inverter circuits particularly for use in highly accurate measuring devices such as LSI testers.

[0002] 2. Description of the Related Art

[0003] Recently, a variety of electronic devices have been using ICs and LSI devices, in which integrated circuits are frequently composed of CMOS circuits (where “CMOS” stands for “Complementary Metal Oxide Semiconductor”) in order to reduce electric power consumption. A typical example of an inverter circuit using CMOS circuits is composed of p-channel transistors and n-channel transistors. FIG. 5 shows an example of the CMOS-type inverter circuit. That is, an inverter circuit 10 is a combination of unit inverters 20a, 20b, . . . , which are combined together in a cascade connection manner. Normally, several tens of the unit inverters are connected together in a cascade connection manner to form the inverter circuit.

[0004] The unit inverter 20a has a p-channel MOS transistor (hereinafter, referred to as a PMOS transistor) 21 a and an n-channel MOS transistor (hereinafter, referred to as an NMOS transistor) 22a. Both the gate electrode of the PMOS transistor 21a and the gate electrode of the NMOS transistor 22a are connected to an input terminal 23a.

[0005] Both the drain electrode of the PMOS transistor 21a and the source electrode of the NMOS transistor 22a are connected to an output terminal 24a. In addition, the source electrode of the PMOS transistor 21a is connected to a power source (Vcc), and the drain electrode of the NMOS transistor 22a is grounded.

[0006] The unit inverter 20b is formed similarly to the unit inverter 20a. Specifically, the unit inverter 20b has a PMOS transistor 21b and an NMOS transistor 22b. Both the gate electrode of the PMOS transistor 21b and the gate electrode of the NMOS transistor 22b are connected to an input terminal 23b. Both the drain electrode of the PMOS transistor 21b and the source electrode of the NMOS transistor 22b are connected to an output terminal 24b. In addition, the source electrode of the PMOS transistor 21b is connected to the power source (Vcc), and the drain electrode of the NMOS transistor 22b is grounded.

[0007] The aforementioned unit inverters 20a and 20b are combined together in a cascade connection manner such that the output terminal 24a is connected to the input terminal 23b.

[0008] Next, the operation timings of the inverter circuit 10 shown in FIG. 5 will be described with reference to the time charts shown in FIGS. 6A to 6D. A clock signal CLK1 shown in FIG. 6A is input to the input terminal 23a of the unit inverter 20a. Herein, it is possible to vary the frequency of the clock signal CLK1 by units of a minimal period. For example, the minimal period (or minimal cycle) of the clock signal CLK1 is approximately set in a range from 2 ns to 10 ns.

[0009]
FIG. 6B shows a transient current I1 such as a charging current, discharging current, and through current that flows in the unit inverter 20a every time the PMOS transistor 21a and the NMOS transistor 22a are switched over; FIG. 6C shows a junction temperature tj; and FIG. 6D shows a time difference tpd measured between the input signal and the output signal of the inverter circuit 10 shown in FIG. 7. In other words, the reference symbol tpd designates the response time of the inverter circuit 10.

[0010] During the time period between time t31 and t34, the clock signal CLK1 is increased in frequency. Therefore, clock pulses are sequentially input to the unit inverter 20a at the minimal periods (T1), each of which approximately ranges from 2 ns to 10 ns. During the aforementioned time period between time t31 and time t34, the PMOS transistor 21a and the NMOS transistor 22a repeat switching operations at a high speed. As a result, an average current IAV, which is an average of the transient current I1 shown in FIG. 6B during the aforementioned time period, flows across both the PMOS transistor 21a and the NMOS transistor 22a.

[0011] In the above, the junction temperature tj (see FIG. 6C) that is initially set to 25° C. is gradually increased to 75° C. due to clock pulses sequentially input to the unit inverter 20a. Accordingly, the response time tpd (see FIG. 6D) that is initially set to 1600 ps is increased to 2000 ps due to clock pulses sequentially input to the unit inverter 20a. FIGS. 6C and 6D show that the junction temperature tpd becomes 75° C., and the response time tpd becomes 2000 ps while the PMOS transistor 21a and the NMOS transistor 22a perform high-speed switching operations. These values are merely examples and are not restrictive, and could be easily varied by heat radiation or dissipation using a heatsink, for example.

[0012] During the time period T2 between time t34 and time t35, the clock signal CLK1 is decreased in frequency, wherein only a single clock pulse may be input to the unit inverter 20a within 10 ms, for example. During this time period T2, both the PMOS transistor 21a and the NMOS transistor 22a perform a switching operation one time. Therefore, substantially no transient current flows across the PMOS transistor 21a and the NMOS transistor 22a. For this reason, the junction temperature tj that was increased to 75° C. at time t34 is decreased to 25° C., which is the initial junction temperature of the inverter circuit 10 when input the clock signal CLK1 is not input. Accordingly, the response time tpd that was increased to 2000 ps at time t34 is decreased to 1600 ps, which is the initial response time of the inverter circuit 10 when the clock signal CLK1 is not input.

[0013] During the high-speed operation period (e.g., the foregoing time period between time t31 and t34 shown in FIGS. 6A to 6D), the transient current flows across the PMOS transistor 21a and the NMOS transistor 22a in the unit inverter 20a. In contrast, during the low-speed operation period (e.g., the time period between time t34 and time t35), substantially no transient current flows across the transistors 21a and 22a in the unit inverter 20a. The unit inverter 20b operates similarly to the unit inverter 20a.

[0014] Therefore, the unit inverter 20a may cause dispersions in electric power consumption in response to the frequency of the clock signal CLK1. For this reason, a temperature difference of 50° C. is caused with respect to the junction temperature tj between the high-speed operation period and low-speed operation period. In addition, a response time difference of 400 ps is caused with respect to the response time tpd between the high-speed operation period and low-speed operation period.

[0015] The aforementioned response time difference causes jitter. In a highly accurate measuring device such as an LSI tester, it is necessary to reduce the jitter so as to be not greater than 200 ps in conformity with the requirements of the prescribed standard. However, the aforementioned inverter circuit, which causes relatively large jitter, may be inappropriate for use in a highly accurate measuring device.

SUMMARY OF THE INVENTION

[0016] It is an object of the invention to provide an inverter circuit that causes substantially no variations in junction temperature and jitter even though the clock frequency is varied. Hence, the inverter circuit of this invention is designed to be suitable for use in a highly accurate measuring device.

[0017] An inverter circuit of this invention is designed to be suitable for use in a highly accurate measuring device such as an LSI tester. Specifically, the inverter circuit comprises unit inverters, switching circuits, and a D flip-flop. All of the unit inverters and switching circuits comprise a pair of a PMOS transistor and an NMOS transistor. Additionally, the switching circuits are arranged relative to the unit inverters that are connected together in a cascade connection manner.

[0018] In the above, a clock signal (CLK1) consisting of clock pulses having a variable frequency is input to the unit inverter, while another clock signal (CLK3) having a constant frequency is input to the D flip-flop to produce a prescribed clock signal (CLK2, CLK4). Thus, the D flip-flop is capable of continuously supplying the prescribed clock signal to the switching circuits even when no clock pulse is input to the unit inverter. Thus, it is possible to avoid unwanted variations of junction temperature and response time (e.g., jitter).

[0019] Various configurations for the D flip-flop and switching circuits are provided. According to a first configuration, the gate electrode of the PMOS transistor is grounded, and the inverted output of the D flip-flop is supplied to the gate electrode of the NMOS transistor. According to a second configuration, the output of the D flip-flop is supplied to the gate electrode of the PMOS transistor, and a power voltage (Vcc) is applied to the gate electrode of the NMOS transistor. According to a third configuration, the output of the D flip-flop is supplied to the gate electrode of the PMOS transistor, and the inverted output is supplied to the gate electrode of the NMOS transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] These and other objects, aspects, and embodiments of the present invention will be described in more detail with reference to the following drawing figures, in which:

[0021]
FIG. 1 is a circuit diagram showing a configuration of an inverter circuit in accordance with a first embodiment of the invention;

[0022]
FIG. 2A is a time chart showing a clock signal CLK1 input to a unit inverter of the inverter circuit;

[0023]
FIG. 2B is a time chart showing a clock signal CLK3 input to a D flip-flop provided in the inverter circuit;

[0024]
FIG. 2C is a time chart showing a clock signal CLK2 output from the D flip-flop in the inverter circuit:

[0025]
FIG. 2D is a time chart showing a transient current I1 flowing in the unit inverter of the inverter circuit;

[0026]
FIG. 2E is a time chart showing a switching current I2 flowing a switching circuit of the inverter circuit;

[0027]
FIG. 2F is a time chart showing a total current IT that is the sum of the average of the transient current I1 and the average of the switching current I2;

[0028]
FIG. 2G is a time chart showing a junction temperature tj measured in the inverter circuit;

[0029]
FIG. 2H is a time chart showing a response time tpd of the inverter circuit;

[0030]
FIG. 3 is a block diagram showing a configuration of an inverter circuit in accordance with a second embodiment of the invention;

[0031]
FIG. 4 is a block diagram showing a configuration of an inverter circuit in accordance with a third embodiment of the invention;

[0032]
FIG. 5 is a circuit diagram showing an inverter circuit that comprises unit inverters in a cascade connection manner;

[0033]
FIG. 6A is a time chart showing a clock signal CLK1 consisting of clock pulses, which are changed in frequency over time;

[0034]
FIG. 6B is a time chart showing a transient current I1 flowing across transistors performing switching operations;

[0035]
FIG. 6C is a time chart showing variations of a junction temperature tj measured for the inverter circuit shown in FIG. 5;

[0036]
FIG. 6D is a time chart showing variations of a response time tpd of the inverter circuit shown in FIG. 5; and

[0037]
FIG. 7 is a simplified block diagram showing the inverter circuit shown in FIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] This invention will be described in further detail by way of examples with reference to the accompanying drawings.

[0039]
FIG. 1 is a circuit diagram showing a configuration of an inverter circuit in accordance with a first embodiment of the invention. That is, an inverter circuit 30 shown in FIG. 1 is composed of unit inverters 20a and 20b that are combined together in a cascade connection manner as well as switching circuits 40a and 40b, and a D flip-flop 50. The switching circuits 40a and 40b are provided relative to the unit inverters 20a and 20b respectively. The D flip-flop 50 produces pulses to be supplied to the switching circuits 40a and 40b that are connected in series.

[0040] The unit inverters 20a and 20b shown in FIG. 1 are identical to the foregoing ones shown in FIG. 5, wherein parts identical to those shown in FIG. 5 are designated by the same reference numerals; hence, the description thereof will be omitted. A clock signal CLK1 is input to the unit inverter 20a shown in FIG. 1 similarly to FIG. 5. The switching circuits 40a and 40b are formed in proximity to the unit inverters 20a and 20b respectively. This is because it is necessary to avoid an unwanted reduction of the junction temperature when the clock signal CLK1 is not input to the unit inverters 20a and 20b for a long time, which may range from several milliseconds to several tens of milliseconds, for example. That is, when the clock signal CLK1 is not input to the unit inverters 20a and 20b for a long time, the inverter circuit 30 avoids an unwanted reduction of the junction temperature by forcing current to flow through the switching circuits 40a and 40b respectively.

[0041] The switching circuit 40a has a PMOS transistor 41a and an NMOS transistor 42a. Herein, the drain electrode of the PMOS transistor 41a is connected to the source electrode of the NMOS transistor 42a. The source electrode of the PMOS transistor 41 a is connected to a power source (Vcc), and the drain electrode of the NMOS transistor 42a is grounded. In addition, the gate electrode of the PMOS transistor 41a is grounded, so that the PMOS transistor 41a functions as a load resistance for the NMOS transistor 42a. The D flip-flop 50 is connected to the gate electrode of the NMOS transistor 42a. That is, the D flip-flop 50 is provided to make current flow through the NMOS transistor 42a when the clock signal CLK1 is not input to the unit inverters 20a and 20b for a long time.

[0042] The D flip-flop 50 has a data input terminal (Data) and a clock input terminal (CLK) as well as an inverted output terminal ({overscore (Q)}). That is, the clock signal CLK1 is input to the data input terminal; a clock signal CLK3 is input to the clock input terminal; and a clock signal CLK2 is output from the inverted output terminal. The inverted output (namely, CLK2) of the D flip-flop 50 is supplied to the gate electrode of the NMOS transistor 42a. The switching circuit 40b has a configuration similar to that of the switching circuit 40a and is composed of a PMOS transistor 41b and an NMOS transistor 42b. The clock signal CLK3 has the minimal clock period and consists of clock pulses that appear at a constant rate.

[0043] Generally speaking, the sizes of transistors are defined by the gate widths thereof. In FIG. 1, the sizes of the PMOS transistors 41a and 41b provided in the switching circuits 40a and 40b are set ‘1/n’ times smaller than the sizes of the PMOS transistors 21a and 21b provided in the unit inverters 20a and 20b, wherein ‘n’ is a natural number arbitrarily selected. Similarly, the sizes of the NMOS transistors 42a and 42b provided in the switching circuits 40a and 40b are set ‘1/n’ times smaller than the sizes of NMOS transistors 22a and 22b provided in the unit inverters 20a and 20b. The aforementioned setting for the sizes of the PMOS and NMOS transistors is required in order to match the average current flowing through the unit inverters 20a and 20b with the average current flowing through the switching circuits 40a and 40b. If the same size is set for all the transistors in the unit inverters 20a and 20b as well as the switching circuits 40a and 40b, for example, it may be assumed that the current flowing through the switching circuits 40a and 40b is increased ‘n’ times larger than the current flowing through the unit inverters 20a and 20b.

[0044] The present embodiment is designed to provide the switching circuits 40a and 40b relative to the unit inverters 20a and 20b respectively. That is, the present embodiment avoids an unwanted reduction of the junction temperature by forcing current to flow through the switching circuits 40a and 40b even when no current flows through the unit inverters 20a and 20b for a long time. For this reason, if the average current flowing through the unit inverters 20a and 20b differs from the average current flowing through the switching circuits 40a and 40b, the junction temperature should be varied, and therefore, the original object of this invention cannot be achieved. Specifically, the present embodiment regulates the sizes of the transistors in such a manner that the average current which flows through the unit inverters 20a and 20b performing high-speed switching operations substantially matches the average current which flows through the switching circuits 40a and 40b when substantially no current flows through the unit inverters 20a and 20b. Thus, it is possible to avoid an unwanted reduction of the junction temperature.

[0045] Next, the operations of the inverter circuit 30 of the present embodiment will be described in detail with reference to FIGS. 2A to 2H, which show the operation timings of the inverter circuit 30. In FIG. 1, the clock signal CLK1 is input to an input terminal 23a of the unit inverter 20a. Similar to the aforementioned inverter circuit 10 shown in FIG. 5, the inverter circuit 30 shown in FIG. 1 inputs the clock signal CLK1 whose frequency can be changed in units of one cycle. The minimal period of the clock signal CLK1 ranges from 2 ns to 10 ns, for example. In addition, the clock signal CLK3 input to the D flip-flop 50 has the aforementioned minimal period and consists of clock pulses that appear at a constant rate.

[0046]
FIGS. 2A, 2B, and 2C show the clock signals CLK1, CLK3, and CLK2 respectively. FIG. 2D shows a transient current I1 (e.g., charging current, discharging current, and through current) that flows through the PMOS transistor 21a and the NMOS transistor 22a which perform switching operations in the unit inverter 20a. FIG. 2E shows a switching current I2 that flows through the PMOS transistor 41a and the NMOS transistor 42a which perform switching operations in the switching circuit 40a. FIG. 2F shows a total current IT that is the sum of the average of the transient current I1 and the average of the switching current I2. FIG. 2G shows a junction temperature tj; and FIG. 2H shows a response time tpd of the inverter circuit 30. Definitions of the junction temperature tj and the response time tpd have already been described with reference to FIG. 7.

[0047] During the time period between time t11, and t14, the clock signal CLK1 is increased in frequency, that is, the minimal period thereof ranges from 2 ns to 10 ns, for example. Hence, clock pulses of the clock signal CLK1 are sequentially input to the unit inverter 20a in respective cycles corresponding to the aforementioned minimal period. Hence, the PMOS transistor 21a and the NMOS transistor 22a repeat switching operations at a high speed, so that an average transient current IAV (see FIG. 2D) flows through the PMOS transistor 21a and the NMOS transistor 22a in the unit inverter 20a during the time period between t11 and t14. In this time period, the junction temperature tj is increased to 75° C. (see FIG. 2G), and the response time tpd becomes 2000 ps (see FIG. 2H). The present embodiment describes an example wherein the junction temperature tj becomes 75° C., and the response time tpd becomes 2000 ps while the PMOS transistor 21a and the NMOS transistor 22a perform switching operations at a high speed. Of course, these values may be easily varied by providing heat radiation or dissipation using a heatsink and the like.

[0048] During the next time period T2 between time t14 and time t15, the clock signal CLK1 is decreased in frequency. Hence, only one clock pulse is input to the unit inverter 20a during the prescribed time of about 10 ms. That is, each of the PMOS transistor 21a and the NMOS transistor 22a performs a switching operation one time during the time period T2 between time t14 and time t15. Hence, substantially no transient current flows through the PMOS transistor 21a and the NMOS transistor 22a.

[0049] As for the D flip-flop 50, the clock signal CLK1 is input to the data input terminal (Data), and the ‘constant’ clock signal CLK3 is also input to the clock input terminal (CLK). When the clock signal CLK1 is low for two cycles or more corresponding to the minimal period set for the clock signal CLK3, the clock signal CLK2 output from the inverted output terminal of the D flip-flop 50 becomes high (see FIG. 2C). The high level of the clock signal CLK2 is maintained for a while until the next clock pulse of the clock signal CLK1 is input to the unit inverter 20a. During the high level period of the clock signal CLK2, both of the NMOS transistors 42a and 42b in the switching circuits 40a and 40b are turned ON, so that the average switching current IAV (see FIG. 2E) flows through the PMOS transistors 41a and 41b, and through the NMOS transistors 42a and 42b in the switching circuits 40a and 40b.

[0050] As described above, even though no current flows through the unit inverters 20a and 20b for a long time, the average switching current IAV is forced to flow through the switching circuits 40a and 40b. For this reason, substantially no variations occur in the junction temperature tj; actually, it may be observed from FIG. 2G that a small reduction of 2.5° C. occurs in the junction temperature tj due to disparities of the sizes of the transistors and manufacturing errors. Since substantially no variations occur in the junction temperature Tj substantially no variations occur in the response time tpd; actually, it may be observed from FIG. 2H that a small reduction of 20 ps occurs in the response time tpd. In summary, the inverter circuit of the present embodiment operates in a stable manner in terms of the junction temperature and response time, regardless of the operations of the unit inverters.

[0051] As described above, the present embodiment provides the switching circuits 40a and 40b relative to the unit inverters 20a and 20b so that the prescribed current is forced to flow through the switching circuits 40a and 40b even when the clock signal CLK1 is not input to the unit inverters 20a and 20b for a long time. Thus, it is possible to avoid unwanted variations of the junction temperature tj and unwanted variations of the response time tpd which may cause jitter. In summary, the present embodiment provides an inverter circuit which is suitable for use in a highly accurate measuring device.

[0052] Next, other embodiments of this invention will be described with reference to FIGS. 3 and 4. FIG. 3 shows a configuration of an inverter circuit in accordance with a second embodiment of the invention, wherein parts identical to those shown in FIG. 1 are designated by the same reference numerals. Compared to the foregoing inverter circuit shown in FIG. 1, the inverter circuit 30 shown in FIG. 3 is characterized by the following points.

[0053] (i) The D flip-flop 50 provides an output terminal (Q) for producing a clock signal CLK4 based on the clock signals CLK1 and CLK3, so that the clock signal CLK4 is supplied to the gate electrodes of both PMOS transistors 41a and 41b of the switching circuits 40a and 40b. The clock signal CLK4 is an inversion of the foregoing clock signal CLK2 shown in FIG. 2C.

[0054] (ii) The prescribed power voltage (Vcc) is applied to the gate electrodes of both NMOS transistors 42a and 42b of the switching circuits 40a and 40b.

[0055] In the foregoing inverter circuit shown in FIG. 1, the PMOS transistors 41a and 41b of the switching circuits 40a and 40b function as load resistances. In the inverter circuit 30 shown in FIG. 3, the NMOS transistors 42a and 42b function as load resistances. The overall operation of the inverter circuit 30 shown in FIG. 3 is basically similar to the overall operation of the foregoing inverter circuit shown in FIG. 1. During the time period T2 between time t14 and time t15, both the PMOS transistors 41a and 41b are turned ON, so that switching currents flow through the PMOS transistors 41a and 41b as well as the NMOS transistors 42a and 42b respectively. Thus, it is possible to maintain the junction temperature tj substantially at a constant value.

[0056]
FIG. 4 shows a configuration of an inverter circuit in accordance with a third embodiment of the invention, wherein parts identical to those shown in FIGS. 1 and 3 are designated by the same reference numerals. The inverter circuit 30 shown in FIG. 4 is characterized in that the D flip-flop 50 provides both the output terminal (Q) and the inverted output terminal ({overscore (Q)}). That is, the inverter circuit 30 is characterized by the following points.

[0057] (i) The clock signal CLK4 output from the output terminal of the D flip-flop 50 is input to the gate electrodes of both PMOS transistors 41a and 41b of the switching circuits 40a and 40b.

[0058] (ii) The clock signal CLK2 output from the inverted output terminal of the D flip-flop 50 is input to the gate electrodes of both NMOS transistors 42a and 42b of the switching circuits 40a and 40b.

[0059] In the inverter circuit 30 shown in FIG. 4, when both PMOS transistors 41a and 41b are turned ON, both NMOS transistors 42a and 42b are correspondingly turned ON in the switching circuits 40a and 40b. In addition, when both PMOS transistors 41a and 41b are turned OFF, both NMOS transistors 42a and 42b are correspondingly turned OFF. The period of time in which all the PMOS transistors 41a and 41b and the NMOS transistors 42a and 42b are simultaneously turned ON matches the time period (e.g., T2) in which no current flows through the unit inverters 20a and 20b. Therefore, the inverter circuit of the third embodiment shown in FIG. 4 can demonstrate the same effects as the aforementioned inverter circuit of the second embodiment shown in FIG. 3.

[0060] This invention is not necessarily limited to the aforementioned embodiments; hence, it can be freely modified within the scope of the invention. All the embodiments are designed to use the D flip-flop 50 for generation of a clock signal (or clock signals) to be supplied to the switching circuits 40a and 40b. Such a clock signal supply is not necessarily limited to the D flip-flop 50. Hence, it is possible to use any other circuitry that is capable of providing the prescribed clock signal(s) to the switching circuits 40a and 40b when the clock signal CLK1 is not input to the unit inverters 20a and 20b.

[0061] In summary, this invention provides an inverter circuit that comprises unit inverters, switching circuits, and a clock signal supply. Herein, the switching circuits are arranged relative to the unit inverters respectively. The clock signal supply (e.g., D flip-flop) automatically supplies the prescribed clock signal to the switching circuits when no clock pulse is input to the unit inverters. Therefore, it is possible to obtain the outstanding effect that substantially no variations occur in the junction temperature and response time (jitter) even though the frequency of the clock signal input to the unit inverters is varied. Thus, the inverter circuit can operate in a stable manner regardless of variations of the frequency of the clock signal input to the unit inverters; hence, it is suitable for use in a highly accurate measuring device.

[0062] As this invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, the present embodiments are therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the claims.

Inverter circuit

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