INVERTING CIRCUIT

Abstract

An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to French Patent Application No. 1852165, filed on Mar. 13, 2018, which application is hereby incorporated herein by reference.

TECHNICAL FIELD

The present disclosure generally concerns electronic circuits such as inverting circuits.

BACKGROUND

Inverting circuits, or inverters, are circuits enabling to invert a signal. Such circuits are assemblies comprising transistors.

SUMMARY

The present disclosure generally concerns electronic circuits and, more particularly, logic circuits. Particular embodiments apply to the forming of an inverter.

[000s] An embodiment provides an inverter comprising a Z²-FET switch.

According to an embodiment, a first gate of the Z²-FET switch is coupled to a first terminal of application of a first potential.

According to an embodiment, the Z²-FET switch is of type N.

According to an embodiment, the Z²-FET switch is of type P.

According to an embodiment, the inverter comprises at least two Z²-FET switches.

According to an embodiment, a first switch is an N-type Z²-FET switch and a second switch is a P-type Z²-FET switch.

According to an embodiment, the first switch has its anode coupled to a second terminal of application of a second potential and its cathode coupled to a third terminal of application of a third potential, and the second switch has its anode coupled to the second terminal and its cathode coupled to a fourth terminal of application of a fourth potential.

According to an embodiment, the second potential is a power supply potential.

According to an embodiment, the fourth potential is a reference potential.

According to an embodiment, the reference potential is the ground.

According to an embodiment, each Z²-FET switch comprises a second gate.

According to an embodiment, the second gate is positioned on a surface opposite to a surface having the first gate positioned thereon.

According to an embodiment, the second gate comprises an N-type doped portion and a P-type doped portion.

According to an embodiment, the P-type doped portion is coupled to a fifth terminal of application of a fifth positive potential and the N-type doped portion is coupled to a sixth terminal of application of a sixth negative potential.

According to an embodiment, each Z²-FET switch comprises, on a substrate, an anode region, a cathode region, a P-type doped region separating the anode region from the cathode region, and an insulated gate region positioned on top of and in contact with a portion of the P-type doped region.

The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified cross-section view illustrating an N-type Z²-FET switch;

FIG. 2 is a simplified cross-section view illustrating a P-type Z²-FET switch;

FIG. 3 is an electric diagram of an embodiment of an inverter; and

FIG. 4 is an electric diagram of another embodiment of an inverter.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The same elements have been designated with the same reference numerals in the different drawings. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed.

In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., it is referred to the orientation of the drawings. The terms “approximately”, “substantially”, and “in the order of” are used herein to designate a tolerance of plus or minus 10%, preferably of plus or minus 5%, of the value in question.

In the present description, the term “connected” will be used to designate a direct electric connection, with no intermediate electronic component, for example, by means of a conductive track, and term “coupled” or term “linked” will be used to designate either a direct electric connection (then meaning “connected”) or a connection via one or a plurality of intermediate components (resistor, capacitor, etc.).

FIG. 1 is a cross-section view schematically showing a Z²-FET switch, and more particularly an N-type switch I_N. In FIG. 1, switch I_N is more particularly a double ground plane (DGP) Z²-FET type switch.

Switch I_N is formed inside and on top of a SOI (“Silicon On Insulator”) structure comprising a semiconductor layer 1, currently made of silicon, resting on an insulating layer 3, currently called BOX (for “Buried OXide”) and itself resting on a semiconductor support 5, currently made of silicon. Semiconductor support 5 is used as a back gate BG of switch I_N. An active area is delimited in layer 1 and comprises an anode region A_N and a cathode region K_N (or an anode A_N and a cathode K_N) separated by an intermediate region 11. Anode region A_N is heavily P-type doped (P+) and is located on the left-hand side of FIG. 1. Cathode region K_N is heavily N-type doped (N+) and is located on the right-hand side of FIG. 1. Intermediate region 11 is heavily P type doped (P−) and is located between anode region A_N and cathode region K_N. As an example, the intermediate region may be made of compressed silicon-germanium. Back gate BG is divided into a P-type doped portion BG_P and an N-type doped portion BG_N. As a variation, the back gate might be P-type doped only. Portion BG_P is positioned on the side of anode A_N (on the left-hand side of Figure i) and portion BG_N is positioned on the side of cathode K_N. Portions BG_N and BG_P are separated in FIG. 1 by dotted lines 6. An insulated gate is formed on a portion of layer 11 on the side of anode region 7. The insulated region comprises a gate region FG_N called front gate FG_N made of polysilicon and an insulating layer 15 resting on the portion of layer 11.

The operation of N-type Z²-FET switch I_N will now be described. During an operating phase, a potential is applied to back gate BG. More particularly, portion BG_N is coupled to a terminal of application of a positive potential and portion BG_P is coupled to a terminal of application of a negative potential. Further, a positive potential is applied to front gate FG_N. To turn on switch I_N, a positive potential is applied to anode A_N, after which a pulse at a zero potential is applied to front gate FG_N, which results in attracting electrons under front gate FG_N of switch I_N. Switch I_N thus is in a low-impedance state and is thus on.

FIG. 2 is a cross-section view of a P-type Z²-FET switch I_P. The switch I_P of FIG. 2 is similar to the switch I_N of FIG. 1, and thus switch I_P comprises a semiconductor layer 1 resting on an insulating layer 3 which itself rests on a semiconductor layer 5. Layer 1 is divided into three regions: an anode region A_P, an intermediate region 11, and a cathode region K_P. The back gate and the front gate of switch I_P are respectively designated with references BG and FG_P. The difference between switch I_P and switch I_N is that the insulated gate of switch I_P is formed on a portion of layer 11 on the side of cathode region K_P (on the right-hand side in FIG. 2). The insulated gate then still comprises front gate FG_P and an insulating layer 15 resting on the portion of layer 11. The back gate is divided into two portions, one N-type doped (BG_N) and one P-type doped (BG_P).

The operation of P-type Z²-FET switch I_P will now be described. During an operating phase, back gate BG is coupled to a terminal of application of a potential. More particularly, portion BG_P is coupled to a terminal of application of a positive potential and portion BG_N is coupled to a terminal of application of a negative potential. Further, a zero potential is applied to front gate FG_P. To turn on switch I_P, a zero potential is applied to cathode K_P, after which a pulse at a positive potential is applied to front gate FG_P, which results in attracting holes under front gate FG_P of switch I_P. Switch I_P then is in a low-impedance state and is thus on.

FIG. 3 is an electric diagram of an embodiment of an inverter 20 comprising an N-type Z²-FET switch I_N and a P-type Z²-FET switch I_P.

In FIG. 3, the N-type and P-type Z²-FET switches are symbolized in the form of a diode to which certain connections have been added. The anode of the diode corresponds to the anode of the switch and its cathode corresponds to the cathode of the switch. This symbol comprises connections symbolizing front gate FG_N and the two doped portions of back gate BG_N and BG_P. The connection symbolizing front gate FG_N is positioned on the lateral side (on the left-hand side in FIG. 3) of the diode symbol, on the anode side for the N-type Z²-FET switch and on the cathode side for the P-type Z²-FET switch. The connection symbolizing the N-type doped portion BG_N of the back gate is positioned on the lateral side (on the right-hand side in FIG. 3) of the diode symbol on the anode side. The connection symbolizing the P-type doped portion BG_P of the back gate is positioned on the lateral side (on the right-hand side in FIG. 3) of the diode symbol on the cathode side. Further, to help differentiate the N-type Z² FET switch from the P-type Z²-FET switch, the symbol of the P type Z²-FET switch comprises on the cathode side a black dot.

In inverter 20, switches I_N and I_P are series-connected between a terminal of application of a power supply potential Vdd and a terminal of application of a reference potential Vss, for example, the ground. More particularly, the anode of switch I_N is coupled, preferably connected, to the terminal of application of potential Vdd and the cathode of switch I_N is coupled, preferably connected, to an output terminal supplying an output potential Vout. The anode of switch I_P is coupled, preferably connected, to the output terminal supplying output potential Vout and the cathode of switch I_P is coupled, preferably connected, to the terminal of application of reference potential Vss. The front gates of switches I_N and I_P are coupled, preferably connected, to a terminal of application of an input potential V_in. The N-type doped portions of the back gates of switches I_N and I_P are coupled, for example, connected, to a terminal of application of a positive potential V_N. The P-type doped portions of the back gates of switches I_N and I_P are coupled, for example, connected, to a terminal of application of a negative potential V_P.

Since the cathode of switch I_P receives the reference potential (Vss), generally zero, a positive pulse on input potential Vin turns on switch I_P. The output potential is then equal to potential Vss.

Since the anode of switch I_N receives the positive potential (Vdd), a negative or zero pulse on input potential Vin turns on switch I_N. The output potential is then equal to potential Vdd.

FIG. 4 is an electric diagram of an embodiment of an inverter 30 comprising a Z²-FET switch I_N and of an N-channel MOS transistor T. Inverter 30 is similar to inverter 20, with the difference that switch I_P is replaced with transistor T.

When input potential Vin is positive, transistor T turns on and the output potential is then equal to potential Vss.

Since the anode of switch I_N receives a positive potential (Vdd), a negative or zero pulse on input potential Vin turns on switch I_N. The output potential is then equal to potential Vdd.

As a variation, based on the structure of FIG. 3, switch I_N may be replaced with a P-channel MOS transistor.

As usual, the following terms are used:

lightly-doped semiconductor layer designates a layer having a dopant atom concentration in the range from 10¹⁴ to 5×10¹⁵ atoms/cm³;

heavily-doped semiconductor layer designates a layer having a dopant atom concentration in the range from 10¹⁷ to 10¹⁸ atoms/cm³; and

very heavily-doped semiconductor layer designates a layer having a dopant atom concentration in the range from 10¹⁸ to 10²⁰ atoms/cm³.

Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, N-type and P-type Z²-FET switches having a fully lightly P-type doped back gate, also called single ground plane Z²-FET switch, may be used.

Various embodiments with different variations have been described hereabove. It should be noted that those skilled in the art may combine various elements of these various embodiments and variations without showing any inventive step.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.

Claims

1. An inverter comprising: a semiconductor substrate;a Z2-FET switch disposed at a first surface of the semiconductor substrate; anda further switch disposed at the first surface of the semiconductor substrate, the further switch having a current path coupled in series with a current path of the Z2-FET switch between a first reference terminal and a second reference terminal.

2. The inverter of claim 1, wherein the Z2-FET switch includes a first gate coupled to an inverter input terminal.

3. The inverter of claim 1, wherein the Z2-FET switch is of type N.

4. The inverter of claim 1, wherein the Z2-FET switch is of type P.

5. The inverter of claim 1, wherein the further switch comprises a second Z2-FET switch.

6. The inverter of claim 5, wherein the Z2-FET switch is an N-type Z2-FET switch and wherein the further switch is a P-type Z2-FET switch.

7. The inverter of claim 6, wherein the Z2-FET switch has an anode coupled to the first reference terminal and a cathode coupled to an inverter output terminal, and wherein the further switch has an anode coupled to the inverter output terminal and a cathode coupled to the second reference terminal.

8. The inverter of claim 7, wherein the first reference terminal is a power supply terminal.

9. The inverter of claim 7, wherein the second reference terminal is a reference terminal.

10. The inverter of claim 9, wherein the reference terminal is ground.

11. The inverter of claim 5, wherein Z2-FET switch and the further switch each comprise a first gate and a second gate.

12. The inverter of claim 11, wherein the first gate is positioned on an upper surface of the semiconductor substrate and wherein the second gate is positioned on a lower surface of the semiconductor substrate, the lower surface opposite the upper surface.

13. The inverter of claim 11, wherein each second gate comprises an N-type doped portion and a P-type doped portion.

14. The inverter of claim 13, wherein, for the Z2-FET switch and the further switch, the P-type doped portion is coupled to a positive potential and the N-type doped portion is coupled to a negative potential.

15. The inverter of claim 1, wherein the Z2-FET switch comprises: an anode region;a cathode region;a P-type doped region separating the anode region from the cathode region; andan insulated gate region positioned on top of and in contact with a portion of the P-type doped region.

16. The inverter of claim 1, wherein the further switch comprises an MOS FET.

17. An inverter comprising: an N-type Z2-FET switch having a cathode coupled to an inverter output terminal, an anode coupled to a positive reference terminal, a top gate coupled to an inverter input terminal, and a back gate having a P-type doped portion coupled to a positive potential and an N-type doped portion coupled to a negative potential; anda P-type Z2-FET switch having a cathode connected to the cathode of the N-type Z2-FET switch and the inverter output terminal, an anode coupled to a negative reference terminal, a top gate coupled to the inverter input terminal, and a back gate having a P-type doped portion coupled to the positive potential and the N-type doped portion coupled to a negative potential.

18. An inverter comprising: a silicon on insulator substrate having a semiconductor layer overlying an insulating layer that overlies a semiconductor substrate;a first Z2-FET switch having an anode region disposed in the semiconductor layer, a cathode region disposed in the semiconductor layer, a P-type doped region disposed in the semiconductor layer between the anode region and the cathode region, an insulated gate region positioned on top of and in contact with a portion of the P-type doped region, and a back gate disposed in the semiconductor substrate beneath the anode region, cathode and P-type doped region;a second Z2-FET switch having an anode region disposed in the semiconductor layer, a cathode region disposed in the semiconductor layer, a P-type doped region disposed in the semiconductor layer between the anode region and the cathode region, an insulated gate region positioned on top of and in contact with a portion of the P-type doped region, and a back gate disposed in the semiconductor substrate beneath the anode region, cathode and P-type doped region;an input terminal coupled to the gate region of the first Z2-FET switch and to the gate region of the second Z2-FET switch;an output terminal coupled to the cathode region of the first Z2-FET switch and to the cathode region of the second Z2-FET switch;a first reference terminal coupled to the anode region of the first Z2-FET switch; anda second reference terminal coupled to the anode region of the second Z2-FET switch.

19. The inverter of claim 18, wherein the back gate of the first Z2-FET switch comprises a first N-type doped portion and a first P-type doped portion and wherein the back gate of the second Z2-FET switch comprises a second N-type doped portion and a second P-type doped portion.

20. The inverter of claim 19, wherein the first and second P-type doped portions are coupled to a positive potential and wherein the first and second N-type doped portions are coupled to a negative potential.

21. The inverter of claim 18, wherein the first Z2-FET switch is of type N and wherein the second Z2-FET switch is of type P.

22. The inverter of claim 18, wherein the first reference terminal is a power supply terminal and the second reference terminal is a ground terminal.