Claims
- 1. An integrated circuit structure, comprising:
- a single, continuous silicon substrate having a planar upper surface;
- a plurality of oxide regions, having planar upper surfaces, formed on the substrate upper surface and separated by spaces, wherein the oxide regions are wider at a bottom portion in contact with the substrate than at the planar upper surfaces, and wherein the oxide regions have physical characteristics of an oxide material formed from thermal oxidation of porous silicon; and
- a plurality of epitaxial regions in contact with the substrate upper surface and filling the spaces between the oxide regions, wherein the epitaxial regions are wider at an upper portion spaced from the substrate than at a lower portion in contact with the substrate and have upper surfaces coplanar with the oxide region upper surfaces.
- 2. The integrated circuit structure of claim 1, wherein the substrate has a <100> crystallographic orientation and the oxide region sidewalls have a <111> crystallographic orientation.
- 3. The integrated circuit structure of claim 1, wherein the substrate is doped with P-type impurities, and the epitaxial regions are doped with N-type impurities.
Parent Case Info
This is a continuation of application Ser. No. 07/839,946, filed Feb. 21, 1992, now abandoned, which is a division, of application Ser. No. 07/677,649, filed Mar. 28, 1991, now U.S. Pat. No. 5,135,884.
US Referenced Citations (8)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2832152 |
Jan 1979 |
DEX |
Non-Patent Literature Citations (1)
Entry |
Y. Watanabe et al., J. Electrochem. Soc. Solid-State Science and Technology "Formation and Properties of Porous Silicon and Its Application", Oct. 1975, pp. 1351-1354. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
677649 |
Mar 1991 |
|
Continuations (1)
|
Number |
Date |
Country |
Parent |
839946 |
Feb 1992 |
|