The present invention relates in general to passgate circuits, and more particularly to a JFET passgate circuit.
A conventional passgate circuit uses complementary-metal-oxide-semiconductor (CMOS) transistors. In particular, it is made by the parallel combination of an NMOS and a pMOS transistor with the input at the gate of one transistor (nNMOS) being complementary to the input at the gate of the other transistor (pMOS). Because CMOS transistors are enhancement mode devices, the resulting passgate circuit has a high resistivity in an “on” condition. As a result, the conventional passgate circuit may experience a voltage drop from input port to output port, and may operate with an undesirable time delay.
In accordance with the present invention, the disadvantages and problems associated with prior passgate circuits have been substantially reduced or eliminated.
In accordance with one embodiment of the present invention, a pass-gate circuit comprises a first depletion mode n-channel JFET, a depletion mode p-channel JFET, and a second depletion mode n-channel JFET. The first depletion mode n-channel JFET has a first terminal coupled to an input port, a second terminal that receives a first control signal, and a third terminal. The depletion mode p-channel JFET has a first terminal coupled to the third terminal of the first depletion mode n-channel JFET, a second terminal that receives a second control signal, and a third terminal. The second depletion mode n-channel JFET has a first terminal coupled to the third terminal of the depletion mode p-channel JFET, a second terminal that receives the first control signal, and a third terminal coupled to an output port.
In accordance with another embodiment of the present invention, a method for operating a passgate circuit comprises receiving a first control signal at a first depletion mode n-channel JFET coupled to an input port. The method further comprises receiving the first control signal at a second depletion mode n-channel JFET coupled to an output port. The method further comprises receiving a second control signal at a depletion mode p-channel JFET coupled to the first and second depletion mode n-channel JFETs. The JFETs operate such that at least one of the JFETs is turned off if the first control signal is at a low voltage and the second control signal is at a high voltage. The JFETs operate such that each of the JFETs is turned on if the first control signal is at a high voltage and the second control signal is at a low voltage.
The following technical advantages may be achieved by some, none, or all of the embodiments of the present invention.
By using depletion mode transistors such as JFETs rather than enhancement mode devices like CMOS transistors, the current between the input port and output port of the passgate circuit is stronger. As a result, the resistivity of the pass-gate circuit is lower (and the conductivity is higher) than a comparable passgate circuit that uses enhancement mode transistors. In addition, the passgate circuit does not need to use any level translators in order to create appropriate voltages to turn off one or more transistors. Furthermore, the passgate circuit does not experience a voltage drop from the input port to output port due to threshold voltages of the JFETs. Instead, a full rail-to-rail voltage swing is achievable from the input port to the output port. In this regard, whatever voltage that is applied at the input port is communicated to the output port.
These and other advantages, features, and objects of the present invention will be more readily understood in view of the following detailed description, drawings, and claims.
For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions, taken in conjunction with the accompanying drawings, in which:
First depletion mode n-channel JFET 12 comprises a junction field effect transistor having n-type semiconductor material in its channel region. JFET 12 receives first control signal 22 at a gate terminal 40. Depletion mode p-channel JFET 14 comprises a junction field effect transistor having p-type semiconductor material in its channel region. JFET 14 receives second control signal 26 at a gate terminal 42. Second depletion mode n-channel JFET 16 comprises a junction field effect transistor having n-type semiconductor material in its channel region. JFET 16 receives first control signal 22 at a gate terminal 44. Inverter 24 comprises any suitable number and combination of electrical circuit elements that convert a logic low signal to a logic high signal, and a logic high signal to a logic low signal.
First control signal 22 comprises an “enable” signal having a voltage of either zero volts or Vdd. Second control signal 26 comprises an “enable bar” signal having the opposite voltage of signal 22. Thus, if signal 22 is zero volts, then signal 26 comprises Vdd. If signal 22 is at Vdd, then signal 26 is zero volts. In a particular embodiment, Vdd is maintained at a voltage greater than |Vtp|+|Vtn|, where Vtp is the threshold voltage of p-channel JFET 14 and Vtn is the threshold voltage of n-channel JFETs 12 or 16. Input signal 20 comprises a voltage signal that is either zero volts (e.g., logic low) or Vdd (e.g., logic high). Output signal 28 comprises a voltage signal that is either zero volts (e.g., logic low) or Vdd (e.g., logic high).
Referring to row 120, the voltage conditions set forth in columns 106-112 cause JFET 12 to be turned on, JFET 14 to be turned off, and JFET 16 to be turned on. The net effect is that circuit 10 is turned off. Referring to row 122, the voltage conditions set forth in columns 106-112 cause JFET 12 to be turned off, JFET 14 to be turned off, and JFET 16 to be turned on. The net effect is that circuit 10 is turned off. Referring to row 124, the voltage conditions set forth in columns 106-112 cause JFET 12 to be turned on, JFET 14 to be turned off, and JFET 16 to be turned off. The net effect is that circuit 10 is turned off. Referring to row 126, the voltage conditions set forth in columns 106-112 cause JFET 12 to be turned off, JFET 14 to be turned on, and JFET 16 to be turned off. The net effect is that circuit 10 is turned off.
Referring now to row 128, the voltage conditions set forth in columns 106-110 cause each of JFETs 12-16 to be turned on. The net effect is that circuit 10 is turned on. As a result, the logic low of input signal 22 is passed as a logic low to output signal 26. Referring to row 130, the voltage conditions set forth in columns 106-110 cause each of JFETs 12-16 to be turned on. The net effect is that circuit 10 is turned on. As a result, the logic high of input signal 22 is passed as a logic high to output signal 26.
A particular advantage of circuit 10 is that by using depletion mode transistors such as JFETs 12-16 rather than enhancement mode devices like CMOS transistors, the current between input port 30 and output port 32 is stronger. As a result, the resistivity of the circuit 10 is lower (and the conductivity is higher) than a comparable passgate circuit that uses enhancement mode transistors. In addition, circuit 10 does not need to use any level translators in order to create appropriate voltages to turn off one or more transistors. Furthermore, circuit 10 does not experience a significant voltage drop from input port 30 to output port 32 due to threshold voltages of JFETs 12-16. Instead, a substantially full rail-to-rail voltage swing is achievable from input port 30 to output port 32. In this regard, whatever voltage that is applied at input port 30 is communicated to output port 32.
Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the sphere and scope of the invention as defined by the appended claims.