Jitter detection and reduction

Abstract

A method of detecting jitter in a digital data signal having a waveform defined by a plurality of component frequencies, including the step of comparing an indicator of the power of a selected frequency portion of the digital data signal against a reference so as to provide an indicator of the shape of the frequency-power characteristic of the data signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention and to show how the same may be put into effect, reference will now be made, by way of example, to the following drawings in which:

FIG. 1 a shows a predicted spectrum of a PRBS signal at 10 Gbps with rise and fall times of 25 ps and rms jitter of 1.0 ps;

FIG. 1 b shows a predicted spectrum of a PRBS signal at 10 Gbps with rise and fall times of 25 ps and rms jitter of 0.5 ps;

FIG. 1 c shows a predicted spectrum of a PRBS signal at 10 Gbps with rise and fall times of 25 ps and rms jitter of 2.0 ps;

FIG. 1 d shows a predicted spectrum of a PRBS signal at 10 Gbps with rise and fall times of 25 ps and rms jitter of 4.0 ps;

FIG. 2 shows a clock and data recovery system according to a first embodiment of the invention;

FIG. 3 shows a clock and data recovery system according to a second embodiment of the invention;

FIG. 4 shows a clock and data recovery system according to a third embodiment of the invention;

FIG. 5 shows a clock and data recovery system according to a fourth embodiment of the invention;

Claims

1. A method of detecting jitter in a digital data signal having a waveform defined by a plurality of component frequencies, including the step of comparing an indicator of the power of a selected frequency portion of the digital data signal against a reference so as to provide an indicator of the shape of the frequency-power characteristic of the data signal.

2. A method according to claim 1, including the step of comparing an indicator of the power of the data signal at a selected first frequency range about a frequency equal to the data bit rate of the data signal or a multiple thereof against an indicator of the power of the data signal at a selected frequency range lower than the first frequency range.

3. A method of reducing jitter in an output digital data signal generated by a signal processing device from an input digital data signal and having a waveform defined by a plurality of component frequencies, including the steps of comparing a first indicator of the power of a selected frequency portion of the output digital data signal against a reference so as to provide a second indicator of the shape of the frequency-power characteristic of the output digital data signal; and controlling the signal processing device on the basis of the second indicator so as to reduce jitter in the output digital data signal.

4. A method according to claim 3, wherein the signal processing device is a clock and data recovery circuit.

5. A method according to claim 4, wherein the controlling step includes applying a direct current offset voltage to the input data signal to the clock and data recovery circuit, the magnitude of the direct current offset voltage being determined on the basis of the second indicator.

6. A method according to claim 5, wherein the clock and data recovery circuit comprises an oscillator.

7. A method according to claim 6, wherein the controlling step includes adjusting the loop bandwidth of the oscillator on the basis of the second indicator.

8. A method according to claim 3, including the step of comparing an indicator of the power of the data signal at a selected first frequency range about a frequency equal to the data bit rate of the data signal or a multiple thereof against an indicator of the power of the data signal at a selected frequency range lower than the first frequency range.

9. A system for reducing jitter in an output digital data signal generated by a signal processing device from an input digital data signal and having a waveform defined by a plurality of component frequencies, the system including a controller arranged to compare a first indicator of the power of a selected frequency portion of the output digital data signal against a reference so as to provide a second indicator of the shape of the frequency-power characteristic of the output digital data signal, and to control the signal processing device on the basis of the second indicator so as to reduce jitter in the output digital data signal.

10. A system according to claim 9, wherein the signal processing device is a clock and data recovery circuit.

11. A system according to claim 10, wherein the controller further includes a bias-T circuit for applying a direct current offset voltage to the input data signal to the clock and data recovery circuit, the magnitude of the direct current offset voltage being determined on the basis of the second indicator.

12. A system according to claim 10, wherein the clock and data recovery circuit comprises an oscillator.

13. A system according to claim 12, wherein the controller further includes a variable resistor for adjusting the loop bandwidth of the oscillator on the basis of the second indicator.

14. A system according to claim 9, wherein the controller is arranged to compare an indicator of the power of the data signal at a selected first frequency range about a frequency equal to the data bit rate of the data signal or a multiple thereof against an indicator of the power of the data signal at a selected frequency range lower than the first frequency range.

15. A system according to claim 14, wherein the selected first frequency range has a bandwidth of 10% or less than the frequency equal to the data bit rate of the data signal or a multiple thereof.

16. A system according to claim 9, wherein the controller comprises a microprocessor.

17. A system according to claim 9, wherein the controller comprises a closed-loop analogue control circuit.

18. A controller for controlling a signal processing device so as to reduce jitter in an output digital data signal generated by said signal processing device from an input digital data signal and having a waveform defined by a plurality of component frequencies, wherein the controller is arranged to compare a first indicator of the power of a selected frequency portion of the output digital data signal against a reference so as to provide a second indicator of the shape of the frequency-power characteristic of the output digital data signal, and to control the signal processing device on the basis of the second indicator so as to reduce jitter in the output digital data signal.

19. A computer program product comprising program code means which when loaded into a computer controls the computer to carry out the method of claim 1.

20. A method of reducing jitter in an output digital data signal generated by a clock and data recovery device from an input digital data signal and having a waveform defined by a plurality of component frequencies, including the steps of comparing a first indicator of the power of a selected frequency portion of the output digital data signal against a reference so as to provide a second indicator of the depth of a null in the frequency-power characteristic of the output data signal at a frequency equal to the data bit rate of the data signal or a multiple thereof.; and controlling the clock and data recovery device on the basis of the second indicator so as to reduce jitter in the output digital data signal.

21. A system for reducing jitter in an output digital data signal generated by a clock and data recovery device from an input digital data signal and having a waveform defined by a plurality of component frequencies, the system including a controller arranged to compare a first indicator of the power of a selected frequency portion of the output digital data signal against a reference so as to provide a second indicator of the depth of a null in the frequency-power characteristic of the output data signal at a frequency equal to the data bit rate of the data signal or a multiple thereof, and to control the clock and data recovery device on the basis of the second indicator so as to reduce jitter in the output digital data signal.