Patent Application
20200052145
The invention relates to photodetectors in general and particularly to an avalanche photodetector.
Avalanche photodetectors (APD) provide higher sensitivity than p-i-n photodetectors because of the internal gain from avalanche multiplication. APDs are useful in optical receivers for a number of applications. Due to the uncertainties of the total number of impact ionizations, there is amplitude noise on the avalanche gain. The noise is determined by avalanche multiplication material, characterized by the ionization rate ratio between electrons and holes, k. Similar ionization rate between electrons and holes, i.e., k≈1, corresponds to high noise, while low ionization rate between electrons and holes, i.e., k≈0 corresponds to low noise.
Silicon is transparent to the a set wavelengths used in optical fiber communication systems, 1.3 μm-1.6 μm, so epitaxial germanium is typically used for light absorbing material in photodetectors in silicon photonics. However, germanium has a k close to 1, making it a noisy avalanche material. On the other hand, silicon has a very small k<0.1, which is preferable for avalanche. Thus, prior art APDs usually have separate absorption and multiplication regions, as shown in
The electric field in different layers is illustrated in
The conventional prior art APD has a complicated layer structure, which requires multiple epitaxy and doping steps. Typically this type of geometry would be used for vertical incidence detection where light is traveling perpendicular to the plane of the chip. However, integrated optics require waveguide-coupled detectors in which the light is travelling in the plane of the chip. It is difficult to convert the conventional APD structure to work as a waveguide coupled device due to its numerous epitaxial steps.
There is a need for improved avalanche photodiode device structures that allow simpler and less costly fabrication.
According to an aspect of the present invention an avalanche photodetector, comprises: a silicon device layer, comprising: a first electrical contact region including a p dopant, a germanium contact region, an avalanche region, a charge region including the p dopant at a lower level of doping than the first electrical contact region, separating the germanium contact region from the avalanche region, and a second electrical contact region including an n dopant. The avalanche photodetector also comprises: a germanium body in contact with the germanium contact region region; a first electrical terminal in electrical communication with the first electrical contact region; and a second electrical terminal in electrical communication with the second electrical contact region; whereby electrons generated in the germanium body move into the germanium contact region, and then to the avalanche region, while holes generated in the germanium body move to the second electrical contact region.
According to another aspect, a method of fabricating an avalanche photodiode comprises: providing a semiconductor wafer including a silicon device layer; producing a first electrical contact region in the silicon device layer by depositing a p dopant therein; producing a charge region in the silicon device layer including the p dopant at a lower level of doping than the first electrical contact region, producing a germanium contact region adjacent the first contact region and the charge region; producing a second contact region in the silicon device layer including an n dopant, producing an avalanche region adjacent the charge region and the second electrical contact region; depositing a germanium body in contact with the germanium contact region; applying a first electrical terminal in electrical communication with the first electrical contact region; and applying a second electrical terminal in electrical communication with the second electrical contact region.
In one embodiment, the semiconductor wafer is a silicon-on-insulator wafer.
In one embodiment, the first region having a modest doping level has doping that is less than either the p+ doped region or the p++ doped region.
In another embodiment, the second region having a modest doping level has doping that is lower than either the p+ doped region or the p++ doped region.
In another embodiment, the germanium body is in electrical contact with at least one of the p++ doped region, the first region having a modest doping level, and the p+ doped region.
In another embodiment, the first region having a modest doping level is an absorption region.
In yet another embodiment, the second region having a modest doping level is an avalanche region.
In still another embodiment, the germanium body has a non-planar shape.
In a further embodiment, the germanium avalanche photodiode further comprises an oxide layer deposited over the germanium body.
According to another aspect, the invention relates to an improved germanium avalanche photodiode including a semiconductor wafer having a silicon device layer on a surface thereof, a plurality of regions having different doping levels laterally disposed in the silicon device layer, and a germanium body; wherein the improvement comprises: the plurality of regions having different doping levels laterally disposed in the silicon device layer comprising, in order, a p++ doped region, a first region having a modest doping level, a p+ doped region, a second region having a modest doping level, and an n++ doped region; the a germanium body adjacent the silicon device layer; a first electrical terminal in electrical communication with the p++ doped region; and a second electrical terminal in electrical communication with the n++ doped region.
In one embodiment, the first region having a modest doping level has doping that is lower than either the p++ doped region or the p+ doped region.
In another embodiment, the second region having a modest doping level has doping that is lower than either the p++ doped region or the p+ doped region.
In another embodiment, the germanium body is in electrical contact with at least one of the p++ doped region, the first region having a modest doping level, and the p+ doped region.
According to another aspect, the invention relates to a method of making a germanium avalanche photodiode. The method comprises the steps of: providing a semiconductor wafer having a silicon device layer on a surface thereof; creating a plurality of regions having different doping levels in the silicon device layer, the plurality of regions having different doping levels comprising, in order, a p++ doped region, a first region having a modest doping level, a p+ doped region, a second region having a modest doping level, and an n++ doped region; depositing a germanium body adjacent the silicon device layer; providing a first electrical terminal in electrical communication with the p++ doped region; and providing a second electrical terminal in electrical communication with the n++ doped region.
In one embodiment, the method of making a germanium avalanche photodiode further comprises the step of depositing an oxide layer over the germanium body.
In another embodiment, the semiconductor wafer is a silicon-on-insulator wafer.
In yet another embodiment, the germanium body has a non-planar shape.
In another embodiment, the germanium body is in electrical contact with at least one of the p++ doped region, the first region having a modest doping level, and the p+ doped region.
In one embodiment, the first region having a modest doping level has doping that is lower by approximately one order of magnitude than either the p++ doped region or the p+ doped region.
In another embodiment, the second region having a modest doping level has doping that is lower by approximately one order of magnitude than either the p++ doped region or the p+ doped region.
According to another aspect, the invention relates to a method of operating a germanium avalanche photodiode, the germanium avalanche photodiode comprising a semiconductor wafer having a silicon device layer on a surface thereof; a plurality of regions having different doping levels in the silicon device layer, the plurality of regions having different doping levels comprising, in order, a p++ doped region, a first region having a modest doping level, a p+ doped region, a second region having a modest doping level, and an n++ doped region; a germanium body adjacent the silicon device layer; a first electrical terminal in electrical communication with the p++ doped region; and a second electrical terminal in electrical communication with the n++ doped region; the method comprising the steps of: illuminating the germanium body with electromagnetic radiation having an intensity; and measuring an electrical signal at the first and second electrical terminals, the electrical signal representative of the intensity of the electromagnetic radiation.
In one embodiment, the electrical signal is amplified by an avalanche process.
In another embodiment, the substrate is a silicon-on-insulator wafer.
In yet another embodiment, the germanium body has a non-planar shape.
In another embodiment, the germanium body is in electrical contact with at least one of the p++ doped region, the first region having a modest doping level, and the p+ doped region.
In one embodiment, the first region having a modest doping level has doping that is lower by approximately one order of magnitude than either the p++ doped region or the p+ doped region.
In another embodiment, the second region having a modest doping level has doping that is lower by approximately one order of magnitude than either the p++ doped region or the p+ doped region.
According to one aspect, the invention features a germanium avalanche photodiode, comprising: a substrate having a surface; a germanium body adjacent the surface; a first electrical terminal in electrical communication with the germanium body by way of a first surface region of the surface; and a second electrical terminal in electrical communication with the germanium body by way of a second surface region of the surface.
In one embodiment, the substrate is a semiconductor wafer.
In another embodiment, the semiconductor wafer is a silicon-on-insulator wafer that has a silicon device layer on the surface thereof.
In still another embodiment, a plurality of regions having different doping levels in the silicon device layer comprise, in order, a p++ doped region, a first region having a modest doping level, a p+ doped region, a second region having a modest doping level, and an n++ doped region.
In one embodiment, the first region having a modest doping level has doping that is lower by approximately one order of magnitude than either the p++ doped region or the p+ doped region.
In another embodiment, the second region having a modest doping level has doping that is lower by approximately one order of magnitude than either the p++ doped region or the p+ doped region.
In a further embodiment, the germanium body is in electrical contact with at least one of the p++ doped region, the first region having a modest doping level, and the p+ doped region.
In yet a further embodiment, the first region having a modest doping level is an absorption region.
In an additional embodiment, the second region having a modest doping level is an avalanche region.
In one more embodiment, the first surface region of the surface is the p++ doped region of the silicon device layer.
In still a further embodiment, the second surface region of the surface is the n++ doped region of the silicon device layer.
In one embodiment, the germanium body has a non-planar shape.
In another embodiment, the germanium avalanche photodiode further comprises an oxide layer deposited over the germanium body.
The foregoing and other objects, aspects, features, and advantages of the invention will become more apparent from the following description and from the claims.
The objects and features of the invention can be better understood with reference to the drawings described below, and the claims. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the drawings, like numerals are used to indicate like parts throughout the various views.
A list of acronyms and their usual meanings in the present document (unless otherwise explicitly stated to denote a different thing) are presented below.
AMR Adabatic Micro-Ring
APD Avalanche Photodetector
ARM Anti-Reflection Microstructure
ASE Amplified Spontaneous Emission
BER Bit Error Rate
BOX Buried Oxide
CMOS Complementary Metal-Oxide-Semiconductor
CMP Chemical-Mechanical Planarization
DBR Distributed Bragg Reflector
DC (optics) Directional Coupler
DC (electronics) Direct Current
DCA Digital Communication Analyzer
DRC Design Rule Checking
DUT Device Under Test
ECL External Cavity Laser
FDTD Finite Difference Time Domain
FOM Figure of Merit
FSR Free Spectral Range
FWHM Full Width at Half Maximum
GaAs Gallium Arsenide
InP Indium Phosphide
LiNO3 Lithium Niobate
LIV Light intensity(L)-Current(I)-Voltage(V)
MFD Mode Field Diameter
MPW Multi Project Wafer
NRZ Non-Return to Zero
PIC Photonic Integrated Circuits
PRBS Pseudo Random Bit Sequence
PDFA Praseodymium-Doped-Fiber-Amplifier
PSO Particle Swarm Optimization
Q Quality factor
QD Quantum Dot
RSOA Reflective Semiconductor Optical Amplifier
SOI Silicon on Insulator
SEM Scanning Electron Microscope
SMF Single Mode Fiber
SMSR Single-Mode Suppression Ratio
TEC Thermal Electric Cooler
WDM Wavelength Division Multiplexing
We device structure that achieves the same avalanche photodetector function that is found in prior art APDs, but can be easily integrated with waveguides attached to photonic integrated circuits. The electric field in the device is in the plane of the wafer, rather than orthogonal to the wafer. The device structure is compatible with typical silicon photonics process flows. No Ge doping or Metal-Ge direct contact is required. Since the doped regions are fabricated in silicon, in common with those used for fabricating silicon optical modulators, compared to a pure modulator flow, the only significant extra step that is required is germanium epitaxy.
The germanium body 306 is deposited adjacent the silicon device layer 320, for example by epitaxy after all of the doped regions in the silicon device layer 320 are completed. In some embodiments, the region 321 is in electrical contact with the germanium body 306. In some embodiments, the region 322 is in contact electrical with the germanium body 306. In some embodiments, the region 323 is in electrical contact with the germanium body 306. In other embodiments, the germanium body 306 is not in mechanical contact with either or both of regions 321 and 323. The discussion of how the germanium body 306 may be fabricated is described in further detail in co-pending U.S. patent application Ser. No. 14/644,122.
In some embodiments, the regions having a modest doping level may have additional doping added simply as an artifact of the doping of nearby, or adjacent, regions. This additional doping may come about by inaccuracies in locating a dopant deposition or implantation or by diffusion of dopant during an annealing, activation or heat treatment step in the course of ordinary semiconductor processing. In some embodiments, a region having a modest doping level can have an effective doping that is lower than either the p++ doped region 321 or the p+ doped region 323. In some embodiments, a region having a modest doping level can have an effective doping that is lower by approximately one order of magnitude than either the p++ doped region 321 or the p+ doped region 323. In some embodiments, the p-type dopant is boron (B). In some embodiments, the n-type dopants are one or more of phosphorus (P), arsenic (As) and antimony (Sb).
An oxide layer 308 is provided that covers the silicon device layer 320 and the germanium body 306. There are no metal contacts made to the germanium body 306. The electrical contacts to the germanium body 306 are made by way of the p++ doped region 321 on one side and by way of the p+ doped region 323, the region 324 and the n++ doped region 325 on the other side. A voltage is applied to the device such that the electrons that are generated in the Ge body are allowed to move into the region 322, and then to the avalanche region 324, while the holes that are generated in the Ge body are allowed to move to the p++ region 321. Aluminum conductors 310 and 312 are provided to connect the p++ doped region 321 with a p terminal 311 and the n++ doped region 325 with an n terminal 313, respectively, so that the electrical signal generated in the APD can be observed or used. In some embodiments, the conductors 310 and 312 can be fabricated using metals other than aluminum, for example, Cu, W or other common conductor metals.
The device shown in
During germanium epitaxy, the growth rate is different at different crystal orientations. Growth in the <311> crystallographic direction may be slower than growth in the <100> crystallographic direction, thus a triangular (or non-planar) shape may be formed. As used herein, the < > notation is used to identify a family of equivalent directions (i.e., <100> includes the [100] direction, the [010] direction, the [001] direction and their opposite directions, such as [−100]).
The steps used to fabricate the device are to first produce all of the regions 321, 322, 323, 324 and 325 in the silicon device layer, and then provide the oxide layer 308. The Ge body 306 can be deposited in an aperture produced in the oxide layer 308. One or more layers can be deposited over the Ge body to provide mechanical protection and/or optical coatings, such as anti-reflection coatings. The metallization can then be applied.
As shown in the embodiment of
The germanium body 606 is deposited adjacent the silicon device layer 620, for example by epitaxy after all of the doped regions in the silicon device layer 620 are completed. In some embodiments, the region 621 is in electrical contact with the germanium body 606. In some embodiments, the region 622 is in contact electrical with the germanium body 606. In some embodiments, the region 623 is in electrical contact with the germanium body 606. In other embodiments, the germanium body 606 is not in mechanical contact with either or both of regions 621 and 623. The discussion of how the germanium body 606 may be fabricated is described in further detail in co-pending U.S. patent application Ser. No. 14/644,122.
As used herein, the term “a modest doping level” is intended to denote a level of doping that is present in the silicon device layer 620 before any additional doping is deliberately added during processing. In some embodiments, the regions having a modest doping level may in fact have additional doping added simply as an artifact of the doping of nearby, or adjacent, regions. This additional doping may come about by inaccuracies in locating a dopant deposition or implantation or by diffusion of dopant during an annealing, activation or heat treatment step in the course of ordinary semiconductor processing. In some embodiments, a region having a modest doping level can have doping that is lower than either the p++ doped region 621 or the p+ doped region 623. In some embodiments, the p-type dopant is boron (B). In some embodiments, the n-type dopants are one or more of phosphorus (P), arsenic (As) and antimony (Sb). In other embodiments, the n++, p+ or p++ regions can be counter-doped such that an n-type dopant is used in a majority p-type region or a p-type dopant is used in a majority n-type region.
An oxide layer 608 is provided that covers the silicon device layer 620 and the germanium body 606. There are no metal contacts made to the germanium body 606. The electrical contacts to the germanium body 606 are made by way of the p++ doped region 621 on one side and by way of the p+ doped region 623, the region 624 and the n++ doped region 625 on the other side. A voltage is applied to the device such that the electrons that are generated in the Ge body are allowed to move into the region 622, and then to the avalanche region 624, while the holes that are generated in the Ge body are allowed to move to the p++ region 621. Aluminum conductors 610 and 612 are provided to connect the p++ doped region 621 with a p terminal 611 and the n++ doped region 625 with an n terminal 613, respectively, so that the electrical signal generated in the APD can be observed or used. In some embodiments, the conductors 610 and 612 can be fabricated using metals other than aluminum, for example, Cu, W or other common conductor metals.
The device shown in
The steps used to fabricate the device are to first produce all of the regions 621, 622, 623, 624 and 625 in the silicon device layer, and then provide the oxide layer 608. The Ge body 606 can be deposited in an aperture produced in the oxide layer 608. One or more layers can be deposited over the Ge body to provide mechanical protection and/or optical coatings, such as anti-reflection coatings. The metallization can then be applied.
In one embodiment, the Ge body has one or more metal contacts that may conduct current. In another embodiment, the Ge body is doped. In another embodiment, the silicon device layer is partially etched in selected regions. In one embodiment, the Ge body contains, at least partially, a compound containing at least two of silicon, germanium, carbon and tin. In another embodiment, the Ge body is grown using liquid phase epitaxy. In another embodiment, the doping regions are rounded to avoid sharp corners. In another embodiment, the Ge body is rounded to avoid sharp corners. In a further embodiment, the Ge body is grown on partially etched silicon. In a further embodiment, light is incident on the detector from multiple sides. In various embodiments, the germanium is grown using any convenient chemical vapor deposition technique, including, by way of example, ultra high vacuum CVD (UHV-CVD), metallo-organic CVD (MOCVD), plasma enhanced CVD (PEVCD), atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), rapid thermal; CVD (RTCVD) and reduced pressure CVD (RPCVD). In some embodiments, the silicon substrate is doped prior to device fabrication. In various embodiments, the doped regions comprise multiple implants and/or diffusions. In some embodiments, the doped regions vary in doping intensity, for example, being linearly doped. In some embodiments, the doping concentration varies as a function of depth in the silicon. In some embodiments, the dopants are counter-doped using an alternative species. In some embodiments, the Ge body is single crystal or polycrystalline. In some embodiments, the Ge body has a buffer layer (e.g. SiGe, amorphous Ge, SiN) between the silicon device layer and the main Ge body.
In some embodiments, the device will be operated by sending an optical signal to the device's input port. A bias voltage will then be applied across the electrical ports. A larger voltage will result in a larger responsivity and a higher gain. However, a large enough bias voltage will cause avalanche breakdown in which the avalanche process is in a critical regime during which the current is very high and the bandwidth and noise performance are degraded. Electrical controls can be used to operate the avalanche detector at a voltage chosen to maximize performance. The chosen regime may also be a function of the optical input power. Lower input power generally requires a higher gain. The current that flows out of the terminals is then detected.
The device may also be operated in “Geiger mode”, in which the voltage is intentionally increased to be in the breakdown regime. In this mode of operation, a single photon will trigger a self-sustaining current that must then be quenched by some type of circuitry to reset the detector. This mode is efficient at detecting single photons.
The avalanche mechanism is sensitive to temperature. Thus a thermal control may be used with the detector. In some embodiments, the substrate on which the detector sits may be placed onto a thermo-electric cooler. In some embodiments, a heater may be integrated into the detector structure for maximally efficient thermal control. Some embodiments may utilize a heater or a thermoelectric cooler in order to adjust the bandgap energy of the photodetector absorption region. Some embodiments may utilize this heater or thermoelectric cooler in order to control the absorption of the photodetector as a function of input wavelength. Some embodiments may utilize this heater or thermoelectric cooler in order to stabilize the gain or breakdown voltage of the photodetector. Some embodiments may include both a cooler and a heater, which may be operated alone or together, so as to control a range of operation of the device (e.g., the heater operates if the device temperature falls below a lower threshold, and the cooler operates if the device temperature rises above an upper threshold, with the other of the heater or the cooler turned off when the temperature is above the lower threshold and below the upper threshold, respectively).
Methods of designing and fabricating devices having elements similar to those described herein are described in one or more of U.S. Pat. Nos. 7,200,308, 7,339,724, 7,424,192, 7,480,434, 7,643,714, 7,760,970, 7,894,696, 8,031,985, 8,067,724, 8,098,965, 8,203,115, 8,237,102, 8,258,476, 8,270,778, 8,280,211, 8,311,374, 8,340,486, 8,380,016, 8,390,922, 8,798,406, and 8,818,141, each of which documents is hereby incorporated by reference herein in its entirety.
See also the description given in U.S. patent application Ser. No. 14/644,122, filed Mar. 10, 2015, the disclosure of which is hereby incorporated by reference herein in its entirety.
As used herein, the term “optical communication channel” is intended to denote a single optical channel, such as light that can carry information using a specific carrier wavelength in a wavelength division multiplexed (WDM) system.
As used herein, the term “optical carrier” is intended to denote a medium or a structure through which any number of optical signals including WDM signals can propagate, which by way of example can include gases such as air, a void such as a vacuum or extraterrestrial space, and structures such as optical fibers and optical waveguides.
Although the theoretical description given herein is thought to be correct, the operation of the devices described and claimed herein does not depend upon the accuracy or validity of the theoretical description. That is, later theoretical developments that may explain the observed results on a basis different from the theory presented herein will not detract from the inventions described herein.
Any patent, patent application, patent application publication, journal article, book, published paper, or other publicly available material identified in the specification is hereby incorporated by reference herein in its entirety. Any material, or portion thereof, that is said to be incorporated by reference herein, but which conflicts with existing definitions, statements, or other disclosure material explicitly set forth herein is only incorporated to the extent that no conflict arises between that incorporated material and the present disclosure material. In the event of a conflict, the conflict is to be resolved in favor of the present disclosure as the preferred disclosure.
While the present invention has been particularly shown and described with reference to the preferred mode as illustrated in the drawing, it will be understood by one skilled in the art that various changes in detail may be affected therein without departing from the spirit and scope of the invention as defined by the claims.
This application is a continuation of U.S. patent application Ser. No. 16/168,249, filed Oct. 23, 2018, now allowed, which is a continuation of U.S. patent application Ser. No. 15/664,856, filed Jul. 31, 2017, now U.S. Pat. No. 10,134,938, which is a continuation of U.S. patent application Ser. No. 14/818,060, now U.S. Pat. No. 9,755,096, which is a continuation-in-part of U.S. patent application Ser. No. 14/644,122, filed Mar. 10, 2015, now issued U.S. Pat. No. 9,437,759, which application claims priority to and the benefit of then U.S. provisional patent application Ser. No. 61/950,816, filed Mar. 10, 2014, each of which applications is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61950816 | Mar 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16168249 | Oct 2018 | US |
| Child | 16524302 | US | |
| Parent | 15664856 | Jul 2017 | US |
| Child | 16168249 | US | |
| Parent | 14818060 | Aug 2015 | US |
| Child | 15664856 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14644122 | Mar 2015 | US |
| Child | 14818060 | US |
