The present disclosure relates to the field of semiconductor technology, and more particularly, to a layout and a processing method thereof, a storage medium, and a program product.
With the development of semiconductor technologies, integration of semiconductor devices has been continuously improved, and sizes of the semiconductor devices are becoming smaller and smaller. Sizes of memories especially magnetic random access memories (MRAM) need to be further miniaturized to improve the integration of the MRAM. To further improve the integration of the semiconductor devices, layouts of the semiconductor devices need to be further optimized.
In view of the above problems, embodiments of the present disclosure provide a layout and a processing method thereof, a storage medium and a program product, to improve integration of a semiconductor device.
A first aspect of the embodiments of the present disclosure provides a layout having a first memory area and a second memory area at least partially surrounding the first memory area. The layout includes: a base substrate array pattern including a plurality of plug patterns spaced apart; and a storage pattern including a magnetic tunnel junction pattern positioned in the first memory area and a capacitor pattern positioned in the second memory area. The magnetic tunnel junction pattern shares a partially overlapped area with a given one of the plurality of plug patterns positioned in the first memory area, and the capacitor pattern shares a partially overlapped area with a given one of the plurality of plug patterns positioned in the second memory area.
A second aspect of the embodiments of the present disclosure provides a method for processing a layout, where the layout has a first memory area and a second memory area at least partially surrounding the first memory area. The processing method includes: forming, in a blank layout, a base substrate array pattern including a plurality of plug patterns spaced apart; and forming a storage pattern, which includes a magnetic tunnel junction pattern positioned in the first memory area and a capacitor pattern positioned in the second memory area. The magnetic tunnel junction pattern shares a partially overlapped area with a given one of the plurality of plug patterns positioned in the first memory area, and the capacitor pattern shares a partially overlapped area with a given one of the plurality of plug patterns positioned in the second memory area.
A third aspect of the embodiments of the present disclosure provides a storage medium storing computer-executable instructions, where the computer-executable instructions are executable by a processor, whereby the processing method is implemented. The storage medium in the embodiments of the present disclosure is configured to implement the above processing method, and thus at least has the advantages of the above processing method. Reference may be made to the above for concrete effects of the storage medium, and detailed descriptions thereof are omitted here.
A fourth aspect of the embodiments of the present disclosure provides a program product including a computer program, where the computer program is executable by a processor, whereby the processing method is implemented. The program product in the embodiments of the present disclosure is configured to implement the above processing method, and thus at least has the advantages of the above processing method. Reference may be made to the above for concrete effects of the program product, and detailed descriptions thereof are omitted here.
To improve integration of a semiconductor device, the layout in the embodiments of the present disclosure includes a base substrate array pattern and a storage patter. The base substrate array pattern includes a plurality of plug patterns spaced apart, and the storage pattern includes a magnetic tunnel junction pattern positioned in a first memory area and a capacitor pattern positioned in a second memory area. The magnetic tunnel junction pattern shares a partially overlapped area with a given one of the plurality of plug patterns positioned in the first memory area, and the capacitor pattern shares a partially overlapped area with a given one of the plurality of plug patterns positioned in the second memory area. The base substrate array pattern, the magnetic tunnel junction pattern and the capacitor pattern are formed in the layout. Therefore, when the layout is configured for production subsequently, a magnetic random access memory (MRAM) may be fabricated by means of a fabrication process of a dynamic random access memory (DRAM), such that a memory density of the MRAM is improved, and thus the integration of the MRAM is further improved, and the integration of the semiconductor device is improved.
To make the above objectives, features, and advantages of the embodiments of the present disclosure more apparent and lucid, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are merely some but not all of the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.
Referring to
The second memory area 12 at least partially surrounds the first memory area 11. For example, the second memory area 12 completely surrounds the first memory area 11, or the second memory area 12 partially surrounds the first memory area 11. In some embodiments, one edge of the first memory area 11 is partially overlapped with one edge of the second memory area 12. As shown in
Referring to
In some embodiments, as shown in
In a possible example, referring to
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Referring to
As shown in
In some possible embodiments, number of word line patterns 113 intersecting with some of the plurality of active area sub patterns 111 in the same row is two, and the two word line patterns 113 separate these active area sub patterns 111 intersecting therewith into a first contact area 1111 positioned in middle and second contact areas 1112 positioned on two sides of the first contact area 1111. As shown in
It should be noted that part of the plurality of word line patterns 113 may pass through the first memory area 11 and the second memory areas 12 simultaneously, and another part of the plurality of word line patterns 113 may only pass through the second memory areas 12. Number of the plurality of word line patterns 113 passing through the first memory area 11 and the second memory areas 12 simultaneously is at least one. In the one word line pattern 113, a second insulation pattern is also provided between part of the one word line pattern 113 positioned in the first memory area 11 and part of the one word line pattern 113 positioned in the second memory area 12.
In some embodiments, each of the plurality of word line patterns 113 in the second memory areas 12 corresponds to one of the plurality of word line patterns 113 in the first memory area 11, each of the plurality of word line patterns 113 in the second memory areas 12 and the one of the plurality of word line patterns 113 in the first memory area 11 are positioned on a same straight line along the third direction, and between each of the plurality of word line patterns 113 in the second memory areas 12 and the one of the plurality of word line patterns 113 in the first memory area 11 there are provided insulation patterns.
In this way, when each of the plurality of word line patterns 113 is transferred onto the semiconductor substrate to form word lines, insulation is provided between the word lines in the first memory area 11 and the word lines in the second memory areas 12, and the first memory area 11 and the second memory areas 12 may be electrically connected to different control circuits, such that the DRAM and the MRAM can be driven separately, which improves flexibility in control of the semiconductor device. In addition, each of the word lines positioned in the first memory area 11 and one word line positioned in the second memory area 12 are positioned on the same straight line, which facilitates the fabrication of the word lines.
Referring to
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With continued reference to
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In a possible example, as shown in
Each of the plurality of first plug sub patterns 1151 is positioned between adjacent two of the plurality of first data line patterns 114. As shown in
Referring to
The plurality of second plug patterns 115 may be arranged in a hexagonal close-packed structure. That is, every six of the plurality of second plug sub patterns 1152 constitute a group, and a group of second plug sub patterns 1152 encircle into a virtual regular hexagon, where each second plug sub pattern 1152 in a group of second plug sub patterns 1152 is respectively positioned on one vertex of the virtual regular hexagon, to improve an arrangement density of the plurality of second plug sub patterns 1152.
Each of plurality of second plug sub patterns 1152 positioned in the first memory area 11 forms a first electrode contact pattern configured to define a position of the first electrode contact, which may be a bottom electrode contact. Each of plurality of second plug sub patterns 1152 positioned in the second memory area 12 forms a landing pad pattern, which is configured to define a position of a landing pad.
Referring to
The capacitor patterns 116 are positioned in the second memory area 12 and are configured to define positions of capacitors. There are a plurality of capacitor patterns 116 positioned in the second memory area 12, and the plurality of capacitor patterns 116 are spaced apart. The plurality of capacitor patterns 116 are arranged in a hexagonal close-packed structure, and each of the plurality of capacitor patterns 116 shares a partially overlapped area with one landing pad pattern.
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To sum up, the layout in the embodiments of the present disclosure has a first memory area 11 and a second memory area 12 at least partially surrounding the first memory area 11. The layout also includes a base substrate array pattern and a storage pattern, where the base substrate array pattern includes a plurality of plug patterns 115 spaced apart, and the storage pattern includes a plurality of magnetic tunnel junction patterns 121 positioned in the first memory area 11 and a plurality of capacitor patterns 116 positioned in the second memory area 12. Each of the plurality of magnetic tunnel junction patterns 121 shares a partially overlapped area with a given one of the plurality of plug patterns 115 positioned in the first memory area 11, and each of the plurality of capacitor patterns 116 shares a partially overlapped area with a given one of the plurality of plug patterns 115 positioned in the second memory area 12. Each of the plurality of magnetic tunnel junction patterns 121 positioned in the first memory area 11 and the base substrate array pattern may be configured to form patterns of an MRAM, and each of the plurality of capacitor patterns 116 positioned in the second memory area 12 and the base substrate array pattern may be configured to form patterns of a DRAM, such that the layout includes both the patterns of the DRAM and the patterns of the MRAM. That is, the patterns of the DRAM and the patterns of the MRAM are integrated into one layout. When the layout is configured for production subsequently, the MRAM may be fabricated by means of a fabrication process of the DRAM, such that a memory density of the MRAM is improved, and thus the integration of the MRAM is further improved, and the integration of the semiconductor device is improved.
The embodiments of the present disclosure further provide a method for processing a layout. As shown in
Step S100: forming, in a blank layout, a substrate pattern including a plurality of plug patterns spaced apart.
Referring to
forming, in the blank layout, the substrate pattern including a plurality of active area sub patterns spaced apart and extending along the first direction.
Referring to
After the substrate pattern is formed, a plurality of first data line patterns spaced apart and extending along the second direction are formed, where the second direction intersects with the first direction. Each of the plurality of first data line patterns shares a partially overlapped area with each of the plurality of active area sub patterns positioned in the same column.
Referring to
After the plurality of first data line patterns are formed, a plurality of plug patterns positioned between adjacent two of the plurality of first data line patterns are formed, where each of the plurality of plug patterns shares a partially overlapped area with each of the plurality of active area sub patterns.
Referring to
Referring to
Step S200: forming a storage pattern including a magnetic tunnel junction pattern positioned in the first memory area and a capacitor pattern positioned in the second memory area, where the magnetic tunnel junction pattern shares a partially overlapped area with a given one of the plurality of plug patterns positioned in the first memory area, and the capacitor pattern shares a partially overlapped area with a given one of the plurality of plug patterns positioned in the second memory area.
In some possible examples, the forming a storage pattern may include:
forming an initial magnetic tunnel junction pattern covering the base substrate array pattern. Part of the base substrate array pattern is positioned in the first memory area, another part of the base substrate array pattern is positioned in the second memory area, and the initial magnetic tunnel junction pattern covers the entire base substrate array pattern. The initial magnetic tunnel junction pattern is an enclosed pattern, in which no opening or hole is provided.
After the initial magnetic tunnel junction pattern is formed, a first pattern is formed in the initial magnetic tunnel junction pattern positioned in the first memory area, such that the initial magnetic tunnel junction pattern having the first pattern forms a magnetic tunnel junction pattern. Referring to
After the plurality of magnetic tunnel junction patterns are formed, the initial magnetic tunnel junction patterns positioned in the second memory area are removed. Rest of the initial magnetic tunnel junction patterns are removed, the plurality of magnetic tunnel junction patterns are remain, and no other pattern is covered on the base substrate array pattern in the second memory area.
After removing the initial magnetic tunnel junction patterns in the second memory area, an initial capacitor pattern is formed, and the initial capacitor pattern covers the magnetic tunnel junction pattern in the first memory area and the base substrate array pattern in the second memory area. As an enclosed pattern in which no opening or hole is provided, the initial capacitor pattern covers the base substrate array pattern and the magnetic tunnel junction pattern.
After the initial capacitor pattern is formed, a second pattern is formed in the initial capacitor pattern positioned in the second memory area, such that the initial capacitor pattern having the second pattern forms a capacitor pattern. Referring to
After the plurality of capacitor patterns are formed, the initial capacitor patterns positioned in the first memory area are removed. Rest of the initial capacitor patterns are removed, the plurality of capacitor patterns 116 are retained, and no other pattern is covered on the magnetic tunnel junction patterns 121 in the first memory area 11.
To sum up, the layout in the embodiments of the present disclosure has a first memory area 11 and a second memory area 12 at least partially surrounding the first memory area 11. The method for processing a layout includes: forming, in a blank layout, a base substrate array pattern including a plurality of plug patterns 115 spaced apart; and forming a storage pattern, which includes a magnetic tunnel junction pattern 121 positioned in the first memory area 11 and a capacitor pattern 116 positioned in the second memory area 12. The magnetic tunnel junction pattern 121 shares a partially overlapped area with a given one of the plurality of plug patterns 115 positioned in the first memory area 11, and the capacitor pattern 116 shares a partially overlapped area with a given one of the plurality of plug patterns 115 positioned in the second memory area 12. The magnetic tunnel junction patterns 121 positioned in the first memory area 11 and the base substrate array pattern may be configured to form patterns of an MRAM, and the capacitor patterns 116 positioned in the second memory area 12 and the base substrate array pattern may be configured to form patterns of a DRAM, such that the layout formed includes both the patterns of the DRAM and the patterns of the MRAM. When the layout is used for production subsequently, the MRAM may be fabricated by means of a fabrication process of the DRAM, such that a memory density of the MRAM is improved, and thus the integration of the MRAM is further improved, and the integration of the semiconductor device is improved.
In a possible example of the present disclosure, after forming a storage pattern (Step S200), the method further includes:
Step S300: forming an initial conductive pattern covering the magnetic tunnel junction patterns in the first memory area and the capacitor patterns in the second memory area. As an enclosed pattern in which no opening or hole is provided, the initial conductive pattern covers each of the magnetic tunnel junction patterns and each of the capacitor patterns.
Step S400: removing the initial conductive patterns positioned in the first memory area, the initial conductive patterns retained forming conductive patterns. The initial conductive patterns in the first memory area are removed, and the initial conductive patterns in the second memory area are retained. Referring to
Step S500: forming an initial second electrode contact pattern covering each of the magnetic tunnel junction patterns in the first memory area and each of the conductive patterns in the second memory area. As an enclosed pattern in which no opening or hole is provided, the initial second electrode contact pattern covers each of the magnetic tunnel junction patterns and each of the conductive patterns.
Step S600: forming a third pattern in the initial second electrode contact pattern positioned in the first memory area, such that the initial second electrode contact pattern having the third pattern forms each of the plurality of second electrode contact patterns. Referring to
Step S700: removing the initial second electrode contact patterns positioned in the second memory area. Rest of the initial second electrode contact patterns are removed, the plurality of second electrode contact patterns are retained, and no other pattern is covered on the conductive patterns in the second memory area.
In a possible example, as shown in
The embodiments of the present disclosure further provides a storage medium storing computer-executable instructions, and the computer-executable instructions are executable by a processor, whereby the method for processing a layout in any one of the foregoing embodiments of the present disclosure is implemented. The storage medium may be a medium which can store instructions executable by a computer, such as a U disk, a mobile hard disk, a readable memory, a magnetic disk or an optical disk, etc. The storage medium in the embodiments of the present disclosure is configured to implement the above processing method, and thus at least has the advantages of the above method for processing a layout. Reference may be made to the above for concrete effects of the storage medium, and detailed descriptions thereof are omitted here.
The embodiments of the present disclosure further provide a program product including a computer program; the computer program is executable by a processor, whereby the method for processing a layout in any one of the foregoing embodiments of the present disclosure is implemented. The program product in the embodiments of the present disclosure is configured to implement the above method for processing a layout, and thus at least has the advantages of the above method for processing a layout. Reference may be made to the above for concrete effects of the program product, and detailed descriptions thereof are omitted here.
In the above embodiments, the method for processing a layout may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented in software, the method for processing a layout may be implemented, partly or entirely, in the form of a computer program product. The computer program product of the present disclosure includes one or more computer instructions. When the one or more computer program instructions of the present disclosure are loaded and executed on a computer, the flows or functions according to the embodiments of the present disclosure may be generated, partly or entirely. The computer of the present disclosure may be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions of the present disclosure may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions of the present disclosure may be transferred from a website, a computer, a server or a data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium of the present disclosure may be any available medium that can be accessed by a computer or a data storage device that includes one or more available media integrated server, data center, or the like. The medium available in the present disclosure may be magnetic medium (e.g., floppy disk, hard disk, magnetic tape), optical medium (e.g., DVD), or semiconductor medium (e.g., solid state disk (SSD)), and the like.
The embodiments or the implementation manners in this specification are described in a progressive manner. Each of the embodiments is focused on difference from other embodiments, and cross reference is available for identical or similar parts among different embodiments.
In the descriptions of this specification, descriptions of reference terms “one embodiment”, “some embodiments”, “an exemplary embodiment”, “an example”, “one example”, or “some examples” are intended to indicate that features, structures, materials, or characteristics described with reference to the embodiments or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms throughout this specification does not necessarily refer to the same embodiment or example. Furthermore, the features, structures, materials, or characteristics set forth may be combined in any suitable manner in one or more embodiments or examples.
Finally, it should be noted that the foregoing embodiments are merely intended for describing the technical solutions of the present disclosure, but not for limiting the present disclosure. Although the present disclosure is described in detail with reference to the foregoing embodiments, persons of ordinary skill in the art should understand that they may still make modifications to the technical solutions described in the foregoing embodiments or make equivalent replacements to some or all technical features thereof, which does not make corresponding technical solutions in essence depart from the scope of the technical solutions of the embodiments of the present disclosure.
Number | Date | Country | Kind |
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202111444495.3 | Nov 2021 | CN | national |
This application is a continuation of PCT/CN2022/078088, filed on Feb. 25, 2022, which claims priority to Chinese Patent Application No. 202111444495.3 titled “LAYOUT AND PROCESSING METHOD THEREOF, STORAGE MEDIUM, AND PROGRAM PRODUCT” and filed to the State Patent Intellectual Property Office on Nov. 30, 2021, the entire contents of which are incorporated herein by reference.
Number | Date | Country | |
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Parent | PCT/CN2022/078088 | Feb 2022 | US |
Child | 17827778 | US |