Patent Application
20070008014
The present invention relates, in general, to the field of integrated circuit logic circuits and devices. More particularly, the present invention relates to layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit designs of especial utility with respect to integrated circuit devices.
Error correction circuitry (ECC) and other types of logic functions that make use of parity require XOR and the XNOR logic gate functions. These XOR and XNOR gates are more difficult to implement with complementary metal oxide semiconductor (CMOS) technology than standard NAND and NOR logic gates, particularly when considering multi-input gates having more than two inputs. Conventional static three-input XOR circuits are generally slow and require many transistors. Representative implementations of various XOR logic gates are shown, for example, in U.S. Pat. No. 4,749,886 issued Jun. 7, 1988 for “Reduced Parallel Exclusive OR and Exclusive NOR Gate”, U.S. Pat. No. 4,888,499 issued Dec. 19, 1989 for “Three Input Exclusive OR-NOR Gate Circuit” and U.S. Pat. No. 5,936,427 issued Aug. 10, 1999 for “Three-Input Exclusive NOR Circuit”. Examples of conventional four-input XOR circuits are shown, for example, in U.S. Pat. No. 4,570,084 issued Feb. 11, 1986 for “Clocked Differential Cascode Voltage Switch Logic Systems” and U.S. Pat. No. 5,134,616 issued Jul. 28, 1996 for “Dynamic RAM with On-Chip ECC and Optimized Bit and Word Redundancy”. The larger number input XOR gates are important in order to reduce stages in wide-word ECC circuit blocks.
Disclosed herein is a dynamic, multi-input XOR and XNOR logic gate circuit design (as exemplified by representative three and four-input embodiments) utilizing fewer transistors than traditional static designs and, therefore, requiring a smaller amount of integrated circuit layout area while nevertheless affording higher speed operating performance than that exhibited by existing conventional circuits.
Particularly disclosed herein is a logic gate comprising a clocked latch circuit selectively couplable between a supply voltage source and a reference voltage source in response to a first clock signal. The latch circuit has first and second nodes thereof respectively coupled to first and second complementary logic gate outputs. First and second clocked strings of N number of series coupled transistors are selectively couplable between the supply voltage source and the reference voltage source in response to a second clock signal with a selected terminal of each of the N transistors defining first through Nth intermediate nodes therebetween. The logic circuit further comprises N additional transistors with each of the N additional transistors being coupled between one of the intermediate nodes of the first and second clocked strings and a next higher number intermediate node on an opposite one of the first and second clocked strings. The Nth intermediate node of the first and second clocked strings are also selectively couplable to the first and second nodes of said clocked latch circuit in response to the second clock signal and the control terminals of each of the first and second clocked strings of N series coupled transistors and the N additional transistors define logic inputs to the logic gate.
Also particularly disclosed herein is an XOR/XNOR logic gate which comprises a plurality of logic signal inputs and first and second complementary logic signal outputs together with a clocked latch circuit having first and second nodes thereof coupled to the first and second complementary logic signal outputs. The clocked latch circuit is clocked by a first clock signal. The logic gate further comprises a plurality of transistors, with each transistor coupled to receive one of the plurality of logic signal inputs at a control terminal thereof. The plurality of transistors are coupled to first and second intermediate nodes of the logic gate and selectively couplable to the first and second nodes of the clocked latch circuit in response to a second clock signal having an opposite phase with respect to the first clock signal.
The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein:
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P-channel transistor 264 is coupled between VCC and the common connected outputs of transistors 252 and 254, which is also coupled to the gate terminal of another P-channel transistor 268. Similarly, P-channel transistor 268 is coupled between VCC and the common connected outputs of transistors 256 and 258, which is also coupled to the gate terminal of the P-channel transistor 264. The common connected outputs of transistors 252 and 254 is provided through an inverter 266 as the “Q” output while the common connected outputs of transistors 256 and 258 is provided through another inverter 270 as the “/Q”, or XNOR output.
With reference additionally now to
With reference additionally now to
The “Q” output is taken at the common drain terminals of transistors 406, 418, 430, 442, 408, 420, 432 and 444. The “A” input is supplied to the gate terminals of transistors 408, 414, 420 and 426 and its complement, “/A”, is supplied to the gate terminals of transistors 402, 432, 438 and 444. The “B” input is supplied to the gate terminals of transistors 404, 410, 428 and 434 while the complementary “/B” signal is supplied to the gate terminals of transistors 416, 422, 440 and 446. The “C” input is supplied to the gate terminals of transistors 406, 418, 424 and 436 while the complementary “/C” signal is supplied to the gate terminals of transistors 412, 430, 442 and 448. A representative number of inverters for furnishing the “/A”, “/B” and “/C” input signals are also illustrated. As is apparent, the number of transistors required to provide a conventional three-input XOR gate 400 soon grows to be unreasonably large, and possibly prohibitively so for conventional static designs of four or more inputs.
With reference additionally now to
The logic gate 500 is clocked by means of a clock (CLK) signal coupled to line 520 and its complement “CLKB” derived, for example, at the output of a CMOS inverter 522 on line 520B. The CLKB signal is supplied to the gate terminal of transistor 508.
The logic gate 500 comprises first and second strings of series coupled N-channel transistors, with the first string including transistors 526AB, 530BBL and 534CBL while the second string comprises transistors 526A, 530BBR and 534CBR. The first string is selectively couplable to VCC through the enabling of P-channel transistor 524UL and to circuit ground through N-channel transistor 524LL, both of which receive the CLK signal at their gate terminal. Similarly, the second string is selectively couplable to VCC through the enabling of P-channel transistor 524UR and to circuit ground through N-channel transistor 524LR, both of which also receive the CLK signal at their gate terminal.
An N-channel transistor 540BL has its source terminal coupled to a first intermediate node 528R at the drain of transistor 526A and its drain terminal coupled to a second intermediate node 532L at the drain of transistor 530BBL. In like manner, another N-channel transistor 540BR has its source terminal coupled to a first intermediate node 528L at the drain of transistor 526AB and its drain terminal coupled to a second intermediate node 532R at the drain of transistor 530BBR. Further, an N-channel transistor 542CL has its source terminal coupled to the second intermediate node 532R at the drain of transistor 530BBR and its drain terminal coupled to a third intermediate node 536L (“QP”) at the drain of transistor 534CBL. In like manner, another N-channel transistor 542CR has its source terminal coupled to the second intermediate node 532L at the drain of transistor 530BBL and its drain terminal coupled to a third intermediate node 536R (“QPB”) at the drain of transistor 534CBR. The first and second nodes of the latch circuit 502 are selectively couplable to the QP and QPB nodes 536L and 536R through N-channel transistors 538L and 538R respectively, which receive the CLK signal at their gate terminals.
As illustrated the gate of transistor 526A receives the “A” input signal on line 510, the gate terminals of transistors 540BL and 540BR receive the “B” input signal on line 512, while the gate terminals of transistors 542CL and 542CR receive the “C” input signal on line 514. The complementary “AB” signal is supplied to the gate of transistor 526AB on line 510B, the complementary “BB” signal is supplied to the gate of transistors 530BBL and 530BBR on line 512B while the complementary “CB” signal is supplied to the gate of transistors 534CBL and 534CBR on line 514B.
Functionally, when the CLK signal is “low”, the “QP” 536L and “QPB” 536R nodes are precharged “high”, while outputs “Q” 518 and “QB” 518B are disconnected and allowed to remain latched at their previous levels. When the CLK signal transitions to a logic level “high”, inputs “A” 510, “B” 512, “C” 514, “AB” 510B, “BB” 512B and “CB” 514B are evaluated and either node “QP” 536L or “QPB” 536R will go “low”. Since pass gate transistors 538L and 538R are now “on” and coupled to nodes 536L and 536R, this information is transferred to the “Q” 518 and “QB” 518B nodes when the CLK transitions to logic level “low” again, that is, when the complementary CLKB signal goes “high”. The output “Q” and “QB” levels are sensed and amplified through the latch circuit 502 devices.
As previously described, at this time node “QP” 536L and “QPB” 536R are precharged and disconnected from the outputs “Q” 518 and “QB” 518B. The series coupled N-channel transistors 534CBL, 540BL, 530BBL, 526AB, 542CR, 530BBR, 540BR, 534CBR, 526A and 542CL are configured to pull down node “QP” 536L or “QPB” 536R when the CLK signal is “high” according to the three input XOR truth table shown in
With reference additionally now to
Utilizing the principles of the present invention, a four-input XOR/XNOR logic gate 600 can be readily provided through the addition of a “D” input 602 at the gate of additional N-channel transistors 608DL and 608DR and a complementary “DB” input 602B at the gate of additional N-channel transistors 606DBL and 606DBR added to the first and second transistor strings as shown. The transistor 608DR is coupled to an intermediate node 604L at the drain of transistor 534CBL and the “QPQ” node 536R. Similarly, the transistor 608DL is coupled to node 604R at the drain of transistor 534CBR and the “QP” node 536L. Transistor 606DBL is placed in series between transistors 524UL and transistor 534CBL while transistor 606DBR is placed in series between transistors 523UR and 534CBR. The four-input XOR/XNOR logic gate 600 shown operates in a manner analogous to the three-input XOR/XNOR logic gate 500 previously described.
It should be further noted that, while a representative three-input XOR/XNOR logic gate 500 (
While there have been described above the principles of the present invention in conjunction with specific circuit implementations, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
