Patent Application
20100115765
1. Field of the Invention
The present invention relates to a layout verification apparatus, a layout apparatus, a layout verification method, a layout verification program, and a wiring forming method.
2. Description of the Related Art
When a circuit such as a semiconductor integrated circuit is manufactured, a layout pattern thereof is designed first. After that, a photomask (hereinafter, referred simply to as a mask) is created based on the layout pattern. A pattern drawn on the mask is transferred onto a substrate, and thus an actual circuit is obtained.
When the layout pattern is designed, in the first place, positions of a group of primitive cells are determined, and positions of a group of wirings connecting the primitive cells are determined so that a desired circuit operation may be obtained. Thus, layout and wiring data is obtained. A pattern drawn on the mask is not always identical to a pattern formed actually on the substrate due to various factors including an optical proximity effect and the like. Therefore, it is verified whether or not a desired pattern is obtained by using the layout and wiring data. Further, based on a result of the verification, the layout and wiring data is corrected. After that, final verification is performed about whether or not signal communication timings become desired timings. If there is no problem, the layout and wiring data is output as the layout pattern.
A technology related to verification and correction of the layout and wiring data is described in Japanese Patent Application Laid-open No. 2007-12687 (hereinafter, referred to as Patent Document 1). Patent Document 1 describes a design assistance system for a semiconductor integrated circuit, which includes: layout means for determining a layout of a chip by defining a plurality of regions in the chip and layouting and connecting cells, wires, and via holes automatically in each region; production easiness analyzing means for analyzing production easiness of the layout based on an occurrence frequency of defect patterns calculated for each region by reading out defect pattern information and verifying the same with a result of the layout determination; and layout correcting means for correcting the layout of the cells, the wires, and the via holes in the region after selectively extracting the region having the occurrence frequency that is a predetermined value or higher.
In the design assistance system described in Patent Document 1, the result of the determination of the read layout is verified with information of defect patterns when the occurrence frequency of the defect patterns is computed. For performing the verification, it is necessary to prepare the defect pattern information in advance that indicates which layout result becomes a defect pattern. However, it is difficult to cover completely the layout results to be the defect patterns. Therefore, it is considered that the result of the layout determination may include a defect pattern that is not prepared. In this case, the defect part is overlooked. In other words, it is difficult to perform accurate verification by the technology of Patent Document 1.
In order to perform accurate verification, it is considered to simulate a shape of the pattern that is actually formed and to detect the defect part based on a result of the simulation.
As illustrated in
Next, mask data is created based on the layout and wiring data 101, and the mask data is supplied to a verification tool. Here, the mask data is data indicating patterns drawn on the mask. The information indicating a position of the primitive cell is not necessary for the mask data and therefore is eliminated. The verification tool performs an optical proximity correction (OPC) process based on the mask data. As a result of the OPC process, the mask data is delivered as post-OPC data 105. In the post-OPC data 105, a region corresponding to the connection wire 104 and a region corresponding to the terminal 103 are both expressed as a wiring pattern 106.
After that, a shape of the pattern that is actually formed on the substrate is simulated based on the post-OPC data 105 so that post-simulation data 107 is obtained. Based on the post-simulation data 107, verification of an error part is performed. In the example illustrated in
The P&R tool corrects the layout and wiring data 101 based on the correction hint 108. In this case, if the position of the terminal 103 in the primitive cell 102 is changed, the signal communication timing may be shifted so that the final timing verification may not be performed. Therefore, the position of the terminal 103 may not be changed during the correction. However, as described above, the correction hint 108 is created independently of the position of the primitive cell 102. Therefore, the correction hint 108 for moving the position of the terminal 103 may be created. Such the case may not be supported only by correction of the wiring, and therefore the layout of the primitive cell 102 should be performed again. Otherwise, the pattern itself in the primitive cell 102 should be created again. Redoing the layout or the creation of the primitive cell 102 causes an increase of turn around time (TAT).
In other words, there is a problem that if the method of detecting the defect part based on the mask data is used, it becomes difficult to correct the layout and wiring data without changing the position of the terminal included in the primitive cell.
A layout verification apparatus according to the present invention includes: verification means for obtaining mask data indicating a mask pattern to be drawn on a mask based on layout and wiring data indicating positions of a group of primitive cells and positions of connection wires connected to the group of primitive cells, and for verifying a position of the mask pattern based on the mask data, so as to detect an error part; and correction hint creating means for creating correction hint information based on the error part, and for sending the correction hint information to layout and wiring means for correcting the layout and wiring data. The correction hint creating means creates the correction hint information based on terminal information indicating positions of a group of terminals included in the group of primitive cells so that the positions of the group of terminals are not changed by the layout and wiring means.
According to the present invention, the correction hint creating means creates the correction hint information based on the terminal information. Therefore, it is possible to recognize the position at which the terminal exists when the correction hint is created. Thus, it is possible to create the correction hint such that the position of the terminal is not changed. As a result, the layout and wiring data may be corrected without changing the position of the terminal. Thus, the layout and wiring data may be corrected without redoing the layout of the primitive cell.
A layout apparatus according to the present invention includes: the above-mentioned layout verification apparatus; and layout and wiring means for correcting positions of the connection wires in the layout and wiring data based on the correction hint information, so as to output the corrected data as wiring layout data.
A layout verification method according to the present invention includes: obtaining, by a computer, mask data indicating positions of mask regions that are masked when wirings are formed based on layout and wiring data indicating positions of a group of primitive cells and positions of connection wires connected to the group of primitive cells, and verifying the positions of the mask regions based on the mask data, so as to detect an error part; creating, by the computer, correction hint information based on the error part; and sending, by the computer, the correction hint information to layout and wiring means for correcting the layout and wiring data. The creating the correction hint information includes creating the correction hint information based on terminal information indicating positions of a group of terminals included in the group of primitive cells so that the positions of the group of terminals are not changed by the layout and wiring means.
A layout verification program according to the present invention is a program for realizing, by using a computer, the above-mentioned layout verification method.
A wiring forming method according to the present invention includes: correcting positions of the connection wires in the layout and wiring data based on the correction hint information that is sent by the above-mentioned layout verification method, so as to create wiring layout data; manufacturing a mask based on the wiring layout data; and forming wirings by using the mask.
According to the present invention, it is possible to provide a layout verification apparatus, a layout apparatus, a layout verification program, and a wiring forming method, each of which enables correction of the layout and wiring data without changing the position of the terminal even if the method of detecting the defect part based on a result of the simulation is used.
In the accompanying drawings:
Now, an embodiment of the present invention is described with reference to the attached drawings.
As illustrated in
The layout and wiring processing portion 6 and the layout verification apparatus 10 are realized by central processing means (CPU) executing a layout program installed in a computer. In particular, the layout verification apparatus 10 is realized by a layout verification program contained in the layout program. In addition, the layout program is copied from a storage medium such as a digital versatile disk (DVD) and is stored in a read only memory (ROM) of the computer.
Step S10; Perform Layout and Wiring Process
The layout and wiring processing portion 6 performs the layout of a group of primitive cells and the wiring among the primitive cells, and creates the layout and wiring data. Specifically, the layout and wiring processing portion 6 obtains circuit information and refers to a cell library so as to perform the layout and the wiring. The circuit information indicates a group of functional circuits (logic circuits or the like) to be used and a connection relationship among the functional circuits, and the circuit information is prepared in advance. The cell library is a database indicating a pattern forming each of the functional circuits as the primitive cell. The primitive cell is set for each functional circuit. The cell library is also prepared in advance similarly to the circuit information.
The layout and wiring data created by the layout and wiring processing portion 6 is converted into mask data and is sent to the layout verification apparatus 10. The mask data is information indicating a mask pattern to be drawn on a photomask. The mask data is information indicating a region to be shielded from light when exposure is performed and a region through which light may pass when the exposure is performed. In the mask data, the information indicating the position of the primitive cell is lost, and the mask pattern is expressed as graphic data. As the mask data, there is GDS2 data for example.
Step S20; Perform OPC Process
In the layout verification apparatus 10, the OPC portion 1 performs OPC with respect to the mask data, and creates post-OPC data. The post-OPC data is also graphic data similarly to the mask data. The post-OPC data is sent to the lithography simulation portion 2.
Step S30; Perform Lithography Simulation
The lithography simulation portion 2 obtains the post-OPC data and refers to lithography model information so as to perform lithography simulation. The lithography simulation portion 2 determines a shape of the pattern that is actually formed. The determined shape is sent as post-simulation data to the error detection portion 3. The post-simulation data is also graphic data similarly to the mask data. Note that the lithography model information includes information indicating a parameter that affects a shape of the pattern that is actually formed. For instance, the lithography model information includes information indicating step conditions or the like in the lithography step.
Step S40; Detect Error
The error detection portion 3 detects an error part based on the post-simulation data.
Step S50; Acquire Terminal Information
Then, the correction hint creating portion 4 obtains terminal information from the layout and wiring processing portion 6. The terminal information indicates a position of a terminal included within the primitive cell.
Step S60; Create Correction Hint Information
Next, the correction hint creating portion 4 creates the correction hint information indicating the correction hint, based on the error part 8. In this case, the correction hint creating portion 4 recognizes a part of the post-lithography-simulation data corresponding to the terminal as a terminal pattern based on the terminal information. In addition, the correction hint creating portion 4 recognizes parts other than the part corresponding to the terminal as a wiring pattern. Then, the correction hint creating portion 4 creates the correction hint information so that the position of the terminal pattern is not changed. The created correction hint information is sent to the layout and wiring processing portion 6.
Step S70; Correct Layout and Wiring Data
Next, the layout and wiring processing portion 6 performs correction of the layout and wiring data based on the obtained correction hint information. Here, the position of the terminal is not changed, and hence the layout and wiring processing portion 6 changes only the position of the wiring that connects the primitive cells. Therefore, the layout and wiring data may be corrected without redoing the layout of the primitive cell.
Steps S80 and S90; Is There Any Error?
Next, based on the corrected layout and wiring data, the process from Step S20 to Step S40 is performed again, and the error detection portion 3 performs the detection of the error part again. If no error part is detected, the process of the final timing verification and the like is performed with respect to the layout and wiring data, and then layout data is output (Step S90). The output layout data is used for producing a photomask. The mask pattern drawn on the produced photomask is transferred onto the substrate when the actual circuit is manufactured. Thus, the actual circuit is manufactured. On the other hand, if an error part is detected in Step S80, the process of Step S10 and the subsequent steps is performed.
As described above, according to this embodiment, the correction hint creating portion 4 obtains the terminal information so as to recognize which part in the graphic data (post-simulation data) is the pattern corresponding to the terminal. Thus, the correction hint creating portion 4 may create the correction hint information so that the position of the terminal part is not changed. As a result, when the layout and wiring data is corrected, it is not necessary to redo the layout of the primitive cell. Thus, the layout and wiring data may be corrected without increasing the TAT.
Next, an operation of the correction hint creating portion 4 creating the correction hint information is described in detail.
First, an operation performed when the error part 8 is detected between the wiring patterns is described.
In this case, the correction hint creating portion 4 recognizes a wiring pattern 9-3 that is adjacent to the first wiring pattern 9-1 except for the second wiring pattern 9-2. The correction hint creating portion 4 determines a length of a space L1 formed between the wiring pattern 9-3 and the first wiring pattern 9-1. In addition, the correction hint creating portion 4 recognizes a wiring pattern 9-4 that is adjacent to the second wiring pattern 9-2 except for the first wiring pattern 9-1. The correction hint creating portion 4 determines a length of a space L2 formed between the wiring pattern 9-4 and the first wiring pattern 9-2. Then, the correction hint creating portion 4 compares the length of the space L1 with the length of the space L2. If the length of the space L1 is larger than the length of the space L2, the correction hint creating portion 4 creates a correction hint 12 so that a position of the first wiring pattern 9-1 is changed. On the other hand, if the length of the space L2 is larger than the length of the space L1, the correction hint creating portion 4 creates the correction hint 12 so that a position of the second wiring pattern 9-2 is changed. In the example illustrated in
As the length of the space between neighboring wiring patterns is smaller, a short circuit may occur more easily. Therefore, if the position of the second wiring pattern 9-2 is changed in the example illustrated in
Next, an operation performed when the error part 8 is detected between the terminal pattern and the wiring pattern is described.
In the case of the example illustrated in
Next, an operation performed when the error part 8 is detected between the terminal patterns is described.
It is supposed that the error part 8 is detected between a third terminal pattern 14-2 and a fourth terminal pattern 14-3 as illustrated in
Specifically, the correction hint creating portion 4 refers to data before the simulation (mask data or post-OPC data) so as to recognize a pattern 9-6* corresponding to the fourth wiring pattern 9-6. Then, the correction hint creating portion 4 changes the position of the pattern 9-6* in the mask data to be correction candidates 16(1) to 16(n) as illustrated in
Note that the lengths and line widths of the correction candidates 16(1) to 16(n) are determined based on the pattern 9-6*. Specifically, the pattern 9-6* extends linearly from the terminal part and is bent at a midpoint. Therefore, the correction hint creating portion 4 determines the length from the terminal part to the bent part of the pattern 9-6* as a length L. In addition, the correction hint creating portion 4 determines the line width of the pattern 9-6 as a line width W. Then, the correction hint creating portion 4 sets the correction candidate 16 so that the line width and the length become W and L, respectively.
As illustrated in
Next, another operation performed when the error part 8 is detected between the terminal patterns is described.
It is supposed that the error part 8 is detected between a fourth terminal pattern 14-4 and a fifth terminal pattern 14-5 as illustrated in
Specifically, the correction hint creating portion 4 determines a line width W4 of the fourth neighboring pattern 9-7 and a line width W5 of the fifth neighboring pattern 9-8. In addition, the correction hint creating portion 4 determines a space SP1-1 formed between the fourth neighboring pattern 9-7 and the fourth terminal pattern 14-4, and a space SP1-2 formed between the fifth neighboring pattern 9-8 and the fifth terminal pattern 14-5. In addition, the correction hint creating portion 4 recognizes the wiring pattern 9, which is adjacent to the fourth neighboring pattern 9-7 and is not the fourth terminal pattern 14-4, as a fourth pattern 9-9. Similarly, the correction hint creating portion 4 recognizes the wiring pattern 9, which is adjacent to the fifth neighboring pattern 9-8 and is not the fifth terminal pattern 14-5, as a fifth pattern 9-10. Then, the correction hint creating portion 4 determines a space SP2-1 formed between the fourth neighboring pattern 9-7 and the fourth pattern 9-9, and a space SP2-2 formed between the fifth neighboring pattern 9-8 and the fifth pattern 9-10.
Each of the determined values W4, W5, SP1-1, SP1-2, SP2-1, and SP2-2 is a parameter that affects the shape of the terminal pattern 14 in the post-simulation data. Therefore, the correction hint creating portion 4 decides which one of the fourth neighboring pattern 9-7 and the fifth neighboring pattern 9-8 should be set as the alteration wiring pattern based on these parameters. Specifically, the correction hint creating portion 4 computes an evaluation score X-4 for the fourth neighboring pattern 9-7 and an evaluation score X-5 for the fifth neighboring pattern 9-8 in accordance with the following equations (1) and (2).
X-4=(αW4+γSP2-1)/βSP1-1 Equation (1);
X-5=(αW5+γSP2-2)/βSP1-2 Equation (2);
In Equations (1) and (2), α denotes a parameter indicating a weight of the line width W, β denotes a parameter indicating a weight of SP1-1 or SP1-2, and γ denotes a parameter indicating a weight of SP2-1 or SP2-2. The parameters are set in advance in a random access memory (RAM) or the like. It is preferable that the weights have a relationship of “γ>β>α”.
The correction hint creating portion 4 compares the evaluation score X-4 with the evaluation score X-5, and creates the correction hint information so that the position of the part corresponding to the wiring pattern 9 having a larger value is changed in the layout and wiring data.
As illustrated in
Note that, in the example described above, the correction hint creating portion 4 creates the correction hint information by taking into account all the line widths W (W4 and W5), the spaces SP1 (SP1-1 and SP1-2), and the spaces SP2 (SP2-1 and SP2-2). However, it is possible to create the correction hint information by taking into account only the line widths W (W4 and W5). Similarly, it is also possible to create the correction hint information by taking into account only the spaces SP1 (SP1-1 and SP1-2) or to create the correction hint information by taking into account only the spaces SP2 (SP2-1 and SP2-2).
Then, an operation is described with regard to the case where the error part 8 is detected between one wiring pattern and another wiring pattern, and the one wiring pattern is connected to the terminal pattern.
As illustrated in
In this case, the correction hint creating portion 4 creates the correction hint 12 so that the connection between a part corresponding to the wiring pattern 9-11 and a part corresponding to the terminal pattern 14-6 is maintained in the layout and wiring data. Specifically, as illustrated in
In the case of the example illustrated in
As described above, according to this embodiment, the correction hint creating portion 4 obtains the terminal information and creates the correction hint based on the terminal information so that the position of the terminal is not changed. Therefore, despite that the verification is performed based on the mask data that does not contain the information indicating the position of the primitive cell, the layout and wiring data may be corrected without changing the position of the primitive cell. As a result, it is not necessary to create the pattern included in the primitive cell again or to redo the layout of the primitive cell, and hence TAT may be reduced.
| Number | Date | Country | Kind |
|---|---|---|---|
| 290083/2008 | Nov 2008 | JP | national |
