Claims
- 1. An LC element manufacturing method comprising:
- providing a semiconductor substrate;
- forming a first diffusion region and a second diffusion region in the semiconductor substrate;
- forming an insulation layer over the semiconductor substrate;
- forming a gate electrode into one of a spiral, a meander, an arc, a sinusoidal and a circular shape to produce a signal transmission line having a distributed inductance and a distributed capacitance relative to the semiconductor substrate for transmission of signals, the gate electrode being formed over the insulation layer, the gate electrode being formed over at least a portion of the first and second diffusion regions; and
- forming wires over the semiconductor substrate electrically connected to the first and second diffusion regions.
- 2. An LC element manufacturing method comprising:
- providing a semiconductor substrate;
- forming a diffusion region in the semiconductor substrate;
- forming an insulation layer over the semiconductor substrate;
- forming a gate electrode into one of a spiral, a meander, an arc, a sinusoidal and a circular shape to produce a signal transmission line having a distributed inductance and a distributed capacitance relative to the semiconductor substrate for transmission of signals, the gate electrode being formed over the insulation layer, the gate electrode being formed over at least a portion of the diffusion region; and
- forming wires over the semiconductor substrate electrically connected to the signal transmission line gate electrode and the diffusion region.
- 3. The method of claim 1, wherein signals to be transmitted over the signal transmission line is connected to at least one of the gate electrode, a channel, and the gate electrode and the channel.
- 4. The method of claim 2, wherein signals to be transmitted over the signal transmission line is connected to at least one of the gate electrode, a channel, and the gate electrode and the channel.
- 5. An LC element manufacturing method comprising:
- providing a semiconductor substrate;
- forming a first diffusion region and a second diffusion region in the semiconductor substrate;
- forming an insulation layer over the semiconductor substrate;
- forming a gate electrode transmission line include the gate electrode, the gate into one of a spiral, a meander, an arc, a sinusoidal and a circular shape to produce a signal transmission line having a distributed inductance and a distributed capacitance relative to the semiconductor substrate for transmission of signals, the gate electrode having a length and a width being formed over the insulation layer, wherein the length is far greater than the width, the gate electrode being formed over at least a portion of the first and second diffusion regions; and
- forming wires over the semiconductor substrate electrically connected to the first and second diffusion regions.
Priority Claims (4)
Number |
Date |
Country |
Kind |
5-203623 |
Jul 1993 |
JPX |
|
5-294282 |
Oct 1993 |
JPX |
|
5-341476 |
Dec 1993 |
JPX |
|
6-133639 |
May 1994 |
JPX |
|
Parent Case Info
This is a Division of application Ser. No. 08/282,046 filed Jul. 22, 1994, U.S. Pat. No. 5,500,552.
US Referenced Citations (6)
Foreign Referenced Citations (10)
Number |
Date |
Country |
0133799 |
Mar 1985 |
EPX |
0230154 |
Jul 1987 |
EPX |
0596721 |
May 1994 |
EPX |
2509093 |
Jan 1983 |
FRX |
4223937 |
Feb 1993 |
DEX |
59-04144 |
Jan 1984 |
JPX |
2106064 |
Apr 1990 |
JPX |
3190302 |
Aug 1991 |
JPX |
3-259608 |
Nov 1991 |
JPX |
4326607 |
Nov 1992 |
JPX |
Divisions (1)
|
Number |
Date |
Country |
Parent |
282046 |
Jul 1994 |
|