BRIEF DESCRIPTION OF THE DRAWINGS
The above contents of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
FIG. 1 is a cross-sectional diagram of an AlGaInP quaternary light emitting diode in the prior art.
FIG. 2 is a cross-sectional diagram of another AlGaInP quaternary light emitting diode in the prior art.
FIGS. 3A to 3F show the steps of manufacturing the light emitting diode in FIG. 2 via a known wafer bonding technique.
FIGS. 4A to 4C show the process of manufacturing a light emitting diode having a reflective layer in the prior art.
FIGS. 5A to 5G show steps of manufacturing a light emitting diode in FIG. 4 via a wafer bonding technique.
FIG. 6 is a cross-sectional diagram of another light emitting diode having a reflective layer in the prior art.
FIGS. 7A to 7C show the process of manufacturing a light emitting diode having a solder layer in the prior art.
FIGS. 8A to 8G show the steps of manufacturing the light emitting diode in FIG. 7 via a wafer bonding technique.
FIG. 9 is a cross-sectional diagram showing a preferred embodiment of a chip bonding light emitting diode according to the present invention.
FIGS. 10A to 10F show steps of manufacturing the light emitting diode in FIG. 9 via a chip bonding technique according to the present invention.
FIG. 11 is a diagram illustrating the light reflection paths in the light emitting diode according to the present invention when the metal layer is regarded as another reflective layer.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention discloses a chip bonding light emitting diode for fixing the defects of the light emitting diode that is manufactured according to the wafer bonding technique. FIG. 9 is a cross-sectional diagram showing the structure of the chip bonding light emitting diode of the present invention. The chip bonding light emitting diode 500 includes a first electrode 508, a light emitting region 510, an ohmic contact dot 520, a reflective layer 522, a barrier layer 524, a eutectic layer 526, a metal layer 528 served as a second electrode, and a submount 530. The first electrode 508, the light emitting region 510, the ohmic contact dot 520, the reflective layer 522, the barrier layer 524 and the eutectic layer 526 can be regarded as a chip 550. The first electrode 508 and the metal layer 528 are configured as planar electrodes, and the submount 530 is a permanent substrate. Moreover, the surface area of the metal layer 528 is greater than the bottom surface area of the light emitting region 510.
For forming a planar electrode without reducing the efficiency of the light emitting diode, a large-size submount 530 is provided in the present invention, and a plurality of cut chips are placed on the submount 530 for the alloy procedure. The manufacturing procedures are described in the following.
As depicted in FIG. 10A, an n-doped GaAs wafer is provided as a substrate 502, a light emitting region 510 is grown on the substrate 502, and a plurality of first electrodes 508 are formed on the light emitting region 510. The light emitting region 510 at least includes an n-doped AlGaInP layer, an AlGaInP active layer, a p-doped AlGaInP layer, and a p-doped GaP sequentially formed on the n-doped GaAs substrate 502. Typically, the AlGaInP active layer can be a double heterostructure active layer or a quantum well active layer. It is understood that the light emitting region 510 may vary in configurations according to different requirements. It is intended not to limit the structure of the light emitting region in the present invention.
As depicted in FIG. 10B, after the n-doped GaAs substrate is removed, a plurality of ohmic contact dots 520, a reflective layer 522, a barrier layer 524, and a eutectic layer 526 are sequentially formed on the light emitting region 510. In an embodiment, the material of the ohmic contact dot 520 is Ge/Au alloy, and the reflective layer 522 is made of a metal having a high reflectance, e.g. Au, Al or Ag, or a combination of a metal oxide layer and a metal layer having a high reflectance. The metal oxide layer can be served as a reflective layer due to different refraction indexes between the metal oxide and the light emitting diode. Further, the metal oxide layer can avoid an inter-diffusion between the metal layer and the light emitting diode so as to keep the reflection. The barrier layer 524 is made of Pt, Ni, W, or Indium Tin Oxide having a high stability and a high melting point. The eutectic layer 526 is made of Sn, SnAu, SnIn, AuIn, or SnAg alloy having a melting point around 300° C. As depicted in FIG. 1C, the above-described structure in FIG. 10B is cut into a plurality of chips 550.
As depicted in FIG. 10D, a large-size submount 530 is provided, and a metal layer 528 is formed on the submount 530. As depicted in FIG. 10E, the eutectic layer 526 of each cut chip 550 is alloyed with the metal layer 528 around temperature 300° C. As depicted in FIG. 10F, the plurality of the light emitting diodes are obtained after cutting the submount 530 and the metal layer 528.
As depicted in FIG. 10F, the surface area of the cut metal layer 528 is greater than the bottom surface area of the chip 550. The metal layer 528 not covered by the chip 550 is served as a second electrode, and the other portion of the metal layer 528 is used for the alloy procedure and alloyed with the chip 550, thereby electrically connecting the metal layer 528 to the light emitting region 510 of the chip 550.
In addition, the submount 530 and the metal layer 528 can be cut first, and each chip 550 is alloyed with the cut metal layer 528. Therefore, the light emitting diode of the present invention is manufactured, wherein the metal layer 528 is partially covered by the chip 550.
In an embodiment, the metal layer is made of Au, Al, Ag, or a combination thereof. The submount is a permanent substrate made of a high heat conductive and non-electrical conductive material, e.g. AlN.
At last, the metal layer 528 is electrically connected to the light emitting region 510 by alloying the chips 550 with the submount 530 around temperature 300° C. to provide the chip bonding light emitting diode in FIG. 9.
In addition, the permanent substrate of the present invention can be a metal permanent substrate having high heat conductivity. The small-size chips can be directly alloyed with the metal permanent substrate without providing a metal layer on the permanent substrate. The metal permanent substrate can be a Cu substrate.
In addition, the reflective layer, provided by the present invention, is used for reflecting light out the permanent substrate.
In addition, the alloy procedure between the chips and the substrate of the present invention can be processed at a relatively low temperature without degrading the performance of the chips. The alloy temperature is under temperature 300° C. if the eutectic layer is made of Sn20Au80.
In addition, the chips are individually alloyed with the metal layer on the permanent substrate in the present invention, and the length, width, and height of the chips have the same scale level. Therefore, the wafer will not be broken due to insufficient mechanical strength. Even the large-scale light emitting region is broken after the GaAs temporary substrate is removed, the large-scale light emitting region can still be cut into a plurality of chips, and therefore, the yield of the chip bonding light emitting diode of the present invention is amazing.
In addition, as depicted in FIG. 11, because the metal layer 528 on the permanent substrate 530 is partially covered by the chips 550, not only the reflective layer 522 within the chips 550 but also the exposed metal layer 528 can reflect the light generated from the light emitting region 510. Therefore, the efficiency of the light emitting diode is enhanced. Furthermore, the large area of the heat conductive submount is advantageous to heat dissipation, and it is particularly applicable to a high-power light emitting diode.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Patent Application
20070290221
