Patent Application
20140217457
The present invention relates to a light-emitting element chip and a manufacturing method therefor, and particularly relates to a light-emitting element chip using a group III nitride semiconductor and a manufacturing method therefor.
The group III nitride semiconductor, which provides a material for a light-emitting element (LED), can generally be obtained by heteroepitaxially growing it on a substrate (substrate for growth) made of another material. Therefore, the structure of the light-emitting element chip using such material and the manufacturing method therefor are subjected to a restriction. On the other hand, the development of the epitaxial layer lift-off technologies, such as the laser lift-off technology and the chemical lift-off technology, has allowed the substrate to be removed after the growth. Thereby, for the group III nitride semiconductor, the study about the manufacture of a light-emitting element (LED) chip having a vertical structure, which provides electrodes vertically sandwiching the luminescent layer, has been started.
Generally, the group III nitride semiconductor light-emitting element is manufactured by vapor-phase epitaxially growing it on the substrate for growth, such as a sapphire substrate, or the like. In this case, the light-emitting structure portion produced by the vapor-phase epitaxial growth method is thin, and therefore, in the state in which the substrate for growth has been peeled off, it is difficult to handle the light-emitting structure portion as an independent one. Thereby, the light-emitting element chip having the above-mentioned vertical structure requires to be supported by a substrate, or the like, which is different from the substrate for growth, and can replace it.
Patent Document 1 discloses a method which forms a metallic sheet on the p-type nitride semiconductor layer by the plating method, which is followed by dissolving the Si as the substrate for growth. In this case, this metallic sheet serves as a support substrate for the thin semiconductor layer in place of the substrate for growth.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2004-47704
The light-emitting element chip (LED chip) having a vertical structure is generally handled by vacuum-chucking it with the use of a pick-up member (a collet, or the like). Thereby, it is mounted to an LED chip loading member, such as a submount, a lead frame, TO-18, or TO-39, using a conductive adhesive, such as silver paste. Thereafter, the lower electrode of the LED chip and the LED chip loading member are electrically connected to each other, and then electrical connection (wire bonding) between the upper electrode of the LED chip and the LED chip loading member is performed with an Au wire, or the like. Thereby, the LED chip is brought into the state in which it can actually be used as a light-emitting element. These operations are collectively referred to as assembly.
In the case where the uniformity of the emitted light intensity in the light-emitting face can be a problem, as with a large-sized LED chip, the electrode having such a configuration as that which makes the current uniform in the chip is used. As the upper electrode having such a configuration, that with which the bonding pad and the auxiliary electrode formed in the shape of a lattice, an annulus, or a radiation are integrated with each other is often used. On the other hand, the auxiliary electrode is not transparent to the light emitted by an LED, and therefore the portion where this auxiliary electrode is formed obstructs the light, thereby producing a dark portion. Therefore, it is preferable that the auxiliary electrode be thin. In the above-mentioned assembling operation, a flaw or a dent was caused to such a thin auxiliary electrode in some case, leading to a conduction failure.
In addition, it is publicly known that the light taking-out efficiency can be enhanced by providing irregularities on the light-emitting face (the outermost semiconductor surface). And, in the case where such irregularities were provided, the upper electrode (including the auxiliary electrode) was generally formed on the flat face, and only on the irregular surface, a protection film was formed. Even in such case, in the above-mentioned assembling operation, a chip or a crack tended to be produced on the irregular surface and particularly the end portion.
The inventors have proposed an ohmic electrode which is particularly effective if formed on such an irregular surface (International Application No. PCT/JP2010/007611). However, with this ohmic electrode on the irregular surface, particularly such a chip or a dent tended to be produced as compared to the ohmic electrode formed on the ordinary flat face.
In other words, there has been a demand for a light-emitting element chip which has a structure allowing the light-emitting face having an electrode and a light taking-out portion to be protected in the assembly.
The present invention has been made in view of the above-mentioned problem, and it is an object of the present invention to provide a light-emitting element chip which can be assembled safely, and a manufacturing method therefor.
In order to accomplish the above-mentioned purpose, the light-emitting element chip and the manufacturing method therefor in accordance with the present invention is configured as follows:
In other words, the light-emitting element chip is a light-emitting element chip, including a configuration in which a semiconductor layer having a luminescent layer is formed on a conductive supporting portion, the supporting portion being connected to one electrode connected to one face of the semiconductor layer, irregularities being formed on the other face of the semiconductor layer, and the other electrode being formed on the other face, the supporting portion having an outer peripheral portion surrounding the periphery of the other face of the semiconductor layer, with the outer peripheral portion being protruded to above the other face of the semiconductor layer and the other electrode.
The protruded portion formed of a part of this supporting portion is capable of physically protecting the other face of the semiconductor layer and the other electrode.
It is preferable that the protruded top portion of the outer peripheral portion be located higher than the surface of the other electrode by 0.2 μm or over, and further the side face of the semiconductor layer be tapered, being adjacent to the outer peripheral portion of the supporting portion with at least an insulator layer being sandwiched therebetween.
In addition, it is preferable that the supporting portion be integrally formed by a dry or wet deposition method, being made of a metal or an alloy.
In addition, it is preferable that the semiconductor layer be formed of a group III nitride semiconductor, micro surfaces constituting the irregularities on the other face providing a semi-polar plane composed of a group of {10-1-1} planes.
The light-emitting element chip manufacturing method is a light-emitting element chip manufacturing method for manufacturing a plurality of light-emitting element chips using a single growth substrate, including: the epitaxial growth step of sequentially forming a lift-off layer and a semiconductor layer having a luminescent layer on the lift-off layer on the growth substrate; the separation groove forming step of forming, between places corresponding to adjacent light-emitting element chips, a separation groove in which the growth substrate is exposed by removing the semiconductor layer and the lift-off layer; the insulator layer forming step of forming, in the separation groove, an insulator layer which at least surrounds the side face of the semiconductor layer that faces the separation groove; the first electrode forming step of forming one electrode on one face of the semiconductor layer that is the surface thereof on the side opposite to the growth substrate; the supporting portion forming step of forming a supporting portion for supporting the semiconductor layer on the face of the semiconductor layer on the side opposite to the growth substrate, and in the separation groove; the lift-off step of separating the semiconductor layer and the growth substrate from each other by removing the lift-off layer by a wet treatment; the semiconductor layer etching step of etching away the other face of the semiconductor layer that has been exposed by the lift-off step, thereby the supporting portion surrounding the periphery of the other face (the outer peripheral portion of the supporting portion that has been formed in the separation groove) being protruded to above the other face; the irregularities forming step of performing a treatment for forming irregularities on the other face; and the second electrode forming step of forming the other electrode on the other face.
It is preferable that, in the separation groove forming step of the light-emitting element chip manufacturing method, the side face of the semiconductor adjacent to the separation groove be tapered.
In addition, it is preferable that, in the irregularities forming step of the light-emitting element chip manufacturing method, the other face be etched away using an alkaline solution.
Further, it is preferable that, in the supporting portion forming step, the supporting portion be formed such that there exists a thru-hole in the supporting portion; and in the lift-off step, an etchant for etching away the lift-off layer be supplied to the lift-off layer through the thru-hole.
In accordance with the present invention, a light-emitting element chip which can be assembled safely and a manufacturing method therefor can be provided.
Hereinbelow, a light-emitting element chip and a manufacturing method therefor which provide a preferred embodiment of the present invention will be explained with reference to the drawings. In the present invention, the light-emitting element chip means a chip in the state before being assembled, and will be expressed as such for discrimination from the light-emitting element which is produced by assembling it.
One face 12b (the lower face in
In the other face 12d (the upper face in
In addition, on the one face of the semiconductor layer 12, an insulator layer 16 is patterned such that it is symmetrical with the auxiliary electrode 15b in the vertical direction, the semiconductor layer 12 being sandwiched therebetween. With the above-mentioned structure, the current flows in the vertical direction in
In addition, the outer peripheral portion of the supporting portion 11 (the supporting portion outer peripheral portion 11a) surrounds the semiconductor layer 12, being protruded from the other face 12d and the n-side electrode 15 of the semiconductor layer 12, thereby being set at a higher level (on the upper side in
The top portion 11b of the supporting portion outer peripheral portion 11a of the supporting portion 11 is at a level higher than the surface of the n-side electrode 15 by, for example, 0.2 μm. In addition, the place other than the n-side electrode 15 in the surface of the semiconductor layer 12 is covered with a protection film 17.
The semiconductor layer 12 provides a luminescent layer 12a between an n-type GaN based nitride layer (n-type semiconductor layer: n-type layer) 12e and a p-type GaN based nitride layer (p-type semiconductor layer: p-type layer) 12c. The luminescent layer 12a is a layer having a high luminous efficiency, such as a multiple quantum well layer (MQW) composed of, for example, a GaN based nitride layer. The configuration of this semiconductor layer 12 is the same as that which is used with an ordinary LED.
The insulator layer 16 and the protection film 17 are both formed of SiO2, or the like. The supporting portion 11 is made of a material (for example, copper (Cu) or nickel (Ni)) formed by the bonding method or the wet deposition method (such as plating), or the like. The base layer 13 is made of a metal which provides a seed layer for plating, such as nickel (Ni), gold (Au), platinum (Pt), or Cu (for Cu plating), or Ni, paradium (Pd), Au, or Pt (for Ni plating). However, the base layer 13 may be produced as a laminated structure containing these materials as appropriate.
As the material for the p-side electrode 14, a material which can be ohmically connected to the p-type layer 12c, a simple substance metal of, for example, Ag, Rh, Ru, or the like, or an alloy or a laminated structure containing these can be used. Or, an Au—Ni alloy, a simple substance of Pt or Pd, and an alloy of these can also be used. However, the p-side electrode 14 also functions as a light reflection layer, and from this viewpoint, Ag and its alloy family, which have a reflectivity to visible light as high as 85% or over, or Rh and Ru, which have a high reflectivity in the ultraviolet region, are particularly preferably used in accordance with the application. In this case, by using such a material as the material on the side where the p-side electrode 14 is to be contacted with the semiconductor layer 12 (p-type layer 12c), the reflectivity can be increased or the contact resistance can be reduced.
As shown in
In the other face 12d of the semiconductor layer 12, there is formed an irregular structure. The macro surface of the other face 12d (the surface which would be provided if the irregularities are averaged or flattened) is, for example, a (000-1) N polar plane. On the other hand, the micro surface constituting the irregular surface provides a semi-polar plane composed of a group of {10-1.1} planes. In other words, this irregularities are constituted by a semi-polar plane composed of a group of {10-1-1} planes having a minute area. The detail of this point will be explained with the manufacturing method later-described.
As described above, with the light-emitting element chip 10, the supporting portion outer peripheral portion 11a of the supporting portion 11 is protruded to above the other face 12d of the semiconductor layer 12, which has an irregular structure, and the surface of the other electrode 15. Thereby, the n-side electrode 15 (particularly the auxiliary electrode 15b) will not be directly contacted with a collet or the surface of the working bench, and the like, at the time of assembly, thereby the possibility that a flaw or dent may be produced being practically eliminated, whereby occurrence of a conduction failure can be suppressed. Further, occurrence of a chip and initiation of a crack on the irregular surface 12d or in the light-emitting portion of the semiconductor layer 12 can be suppressed. Also, from the viewpoint of protection of the light taking-out face and the light-emitting portion, the assembly can be performed with safety. Herein, as later described, the supporting portion 11 and the supporting portion outer peripheral portion 11a can be integrally formed. The portion which is protruded to above the other face 12d of the semiconductor layer 12 and the n-side electrode (the other electrode) 15 can be formed by bonding a member to the supporting portion 11, however, the manufacturing process will become complicated, and there will be presented a problem with the strength, thereby the bonding scheme is not preferable. By forming the supporting portion 11 and the supporting portion outer peripheral portion 11a integrally, the manufacturing process is simplified with the mechanical strength of the formed portion being able to be increased.
Further, in the case where a conventional flat supporting portion is used, the light which is emitted from the luminescent layer toward the lateral direction was caused to leak in the lateral direction, thereby the light could not be taken out with a sufficient effectiveness. Contrarily to this, with this light-emitting element chip 10, the light which has reached the side face from the luminescent layer 12a is reflected by the supporting portion outer peripheral portion 11a, whereby the light can be taken out with a sufficient effectiveness. In that case, it is preferable that the angle of the tapered portion inside the concave portion of the supporting portion 11 that is contacted with the semiconductor layer 12 through the insulator layer 16 be inclined in the range of from 10° to 80°. How to set this angle will be described later. The taper angle θ in this case is defined as illustrated in
Next, the manufacturing method for the light-emitting element chip 10 according to the present embodiment of the present invention will be explained. The semiconductor layer 12 used for this light-emitting element chip 10 can be obtained by epitaxially growing it on a growth substrate. However, with the light-emitting element chip 10 which is actually manufactured, this growth substrate is removed, and the supporting portion 11, which is different from the growth substrate, is connected on the side opposite to the side where there was the growth substrate. In addition, a number of structures in
First, as shown in
In addition, as the material for the lift-off layer 21, such a metal as chromium (Cr) can be used. Deposition of the lift-off layer 21 can be performed by the sputtering method, the vacuum vapor deposition method, or the like. Before growing the n-type layer 12e after forming the lift-off layer 21, by making a nitriding treatment, such as a heating treatment in the ammonia atmosphere, the lift-off layer 21 can be nitrided to provide, for example, a chromium nitride layer (metal nitride layer: CrN layer). This treatment allows the semiconductor layer 12 having a better characteristic to be obtained, and the later-described lift-off step to be performed easier.
Next, as shown in
In this step, by adjusting the dry etching conditions, such as the type of gas, the pressure thereof, and the etching speed, the anisotropy of the dry etching can be adjusted. By this, the taper angle θ in the end portion of the semiconductor layer 12 can be adjusted. It is preferable that this taper angle θ be between 10° to 80°. Such taper angle adjustment is difficult to be performed in the wet etching, and the wet etching tends to cause the orientation of the slope to be reverse to that in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
The base layer 13 is formed of a material which has a high adherence to the semiconductor layer 12 and the p-side electrode 14, and which can be used as a seed layer in plating. The base layer 13 may have a laminated structure, however, the material at least on the side of the semiconductor layer 12 is preferably a material which can endure the etching at the later-described lift-off step and protection film forming step. Further, if the base layer 13 is to have a high reflectivity as with the p-side electrode 14, it may be provided with a laminated structure having a layer for use as a seed layer, and a reflection layer with a high reflectivity. In this case, as the material for the reflection layer to be provided on the side of the semiconductor layer 12, a platinum family metal, such as Rh or Ru, can be used, and thereon the seed layer can be formed. As the material for the seed layer, it is preferable that, in the case where Ni is to be used as the material for the supporting portion 11 (for Ni plating), Pd be used, while, in the case where Cu is to be used (for Cu plating), Pt/Cu be used. Further, for Ni plating, Ni, Au, Pt, or the like, can be used, and for Cu plating, Ni, Au, Pt, Cu, or the like, can be used. Alternatively, an alloy or a laminated structure based on combination of these metals may be used.
As the material for the supporting portion 11, which is formed by plating, Ni, Cu, Au, or the like, can be used as a material which is different at least from the material for the lift-off layer 21 and the filler 23, and which will not be etched away through the lift-off step. For this plating, either of the dry and wet plating processes can be used, provided that the supporting portion 11 having a sufficient thickness, as depicted in the figure, can be formed. Further, if the wet plating is adopted, either of electroplating and electroless plating can be used.
Next, as shown in
By performing this step, the growth substrate 20 and the semiconductor layer 12 are separated from each other, thereby the bottom face constituted by the n-type layer 12e of the semiconductor layer 12 (the other face) being exposed. This face provides a (000-1) N polar plane, contrarily to the top face of the n-type layer 12e. Hereinafter, since the growth substrate 20 is removed, the supporting portion 11 provides a support substrate for the semiconductor layer 12, and the like. Hereinbelow, as shown in
In this state, as shown in
Next, as shown in
Here, anisotropic wet etching is defined as wet etching with which the etching is selectively progressed for a specific plane orientation. Therefore, in the case where the plane orientation of the macro surface before being subjected to anisotropic etching is different from this specific plane orientation, the surface after the etching is not as flat as that after the semiconductor layer etching step, with a number of irregularities having micro surfaces constituted by a group of planes having such specific plane orientation being formed by the etching. The group of planes having such specific plane orientation can be provided as a group of semipolar {10-1-1} planes, for example.
For such anisotropic wet etching, an alkaline etchant, such as a potassium hydroxide (KOH) solution, a sodium hydroxide (NaOH) solution, or an alkaline solution prepared by mixing of these, can be used. As the solvent, water (H2O) or glycol can be used. In operation, the OH− ion oxidizes the Group-III atom (Ga or Al) in the GaN or AlGaN layer to thereby cause etching. Especially in the case of GaN, there exist three nitrogen atoms under the Ga atom on the Ga polar plane side, and therefore the OH− ion cannot oxidize the Ga atom. On the other hand, on the nitrogen polar plane side, there exists only one nitrogen atom under the Ga atom, whereby the OH− can oxidize the Ga atom. By making such an anisotropic wet etching treatment using an alkaline etchant under a proper condition, such as heating, the (000-1) N polar plane is selectively etched. On the surface after the etching, there are formed a number of hexagonal pyramid-like convexities, which have a hexagonal bottom face, being derived from the hexagonal crystal. For the above-mentioned reason, such anisotropic etching is caused on the nitrogen polar plane, and the Ga polar plane will not substantially be etched, although the same (000-1) plane is provided for both. On the Ga polar plane, if there is a dislocation, the effect of this etching can be observed as a hexagonal pyramid-like pit. The above point is mentioned in the specification of, for example, International Application No. PCT/JP2010/007611.
Since such irregularities are formed, the area of the surface of the n-type layer 12e is approx. double as large as that of the flat nitrogen polar plane (before the anisotropic etching), regardless of the size of the irregularities. Thereby, even if the dimension of the electrode along the planar direction remains unchanged, the effective area of contact with the n-type electrode 15 is increased, which is effective to reduce the value of contact resistance. The size of the irregularities can be controlled by adjusting the concentration of the etchant, the temperature, and the time, and therefore, it is preferable to provide the size which is suitable not only for the above-mentioned reduction in contact resistance, but also for improvement of the efficiency of light taking-out on the basis of the Snell's law. For example, it is preferable that the convex portion constituted by a hexagonal pyramid have a height of 0.3 to 4.5 μm or so.
Next, as shown in
Thereafter, as shown in
Finally, as shown in
By the above-described manufacturing method, a plurality of light-emitting element chips 10 having a configuration as shown in
Here, especially with GaN, and the like, it is generally difficult to obtain a thick p-type layer 12c, and the mobility of a hole is lower than the mobility of an electron, thereby, the resistivity of the p-type layer 12c is generally higher than the resistivity of the n-type layer 12e. Therefore, in order to reduce the forward resistance of the light-emitting element chip, it is preferable that the area of the p-side electrode 14 be large. On the other hand, the light is obstructed by the n-side electrode 15, it is preferable that the area of the electrode provided on the side of the face where the emitted light is taken out be small. Therefore, like the configuration as shown in
In addition, by the above-described manufacturing method, the supporting portion outer peripheral portion 11a is made higher than the light-emitting face (the n-side electrode 15 and the surface of the n-type layer 12e that is covered with the protection film 17), thereby the light-emitting face being protected, which is as described above. In addition, as described above, the above-mentioned irregularities and the electrode configuration allow the electrode resistance to be reduced and the light taking-out efficiency to be enhanced. The effect of the protection is especially remarkable for the above-mentioned configuration, in which the electrode is formed on the irregular surface.
Further, the protruded supporting portion outer peripheral portion 11a also functions as a reflecting mirror which reflects the light emitted in the lateral direction toward the upward direction. Therefore, the luminous efficiency of this light-emitting element chip can be particularly enhanced. In this configuration, the taper angle of the supporting portion outer peripheral portion 11a is equal to the taper angle of the side wall of the semiconductor layer 12. This taper angle θ can be set as appropriate by adjusting the dry etching conditions for the semiconductor layer 12 at the separation groove forming step.
The above-mentioned manufacturing method provides a scheme in which the resist layer 100 is used to form a thru-hole in the supporting portion 11, and in which, at the lift-off step, this thru-hole can be utilized to perform removal of the lift-off layer 21, and the like. This thru-hole is formed in the vertical direction with respect to the lift-off layer 21, thereby the etchant is effectively supplied to the lift-off layer 21, whereby the lift-off layer 21 can be etched away at a high efficiency. Therefore, it is particularly preferable that a thru-hole having such a geometry be provided in the supporting portion 11 before the lift-off step. In addition, by forming this thru-hole, the stress between the supporting portion 11 and the semiconductor layer 12 is relaxed, whereby generation of a crack, and the like, in the semiconductor layer 12 can be suppressed. In the above example, the location of the thru-hole is determined by the location of the insulator layer opening 16a and resist layer 100, however, the forming method and the location are optional, provided that the removal of the lift-off layer 21, and the like, can be performed through the thru-hole.
With the manufacturing method illustrated in
Further, in the above lift-off step, the chemical lift-off method has been used to remove the growth substrate 20. As is well known, as an alternative method for removing the growth substrate 20, the laser lift-off method, which removes the lift-off layer 21 by causing laser light to be absorbed by the lift-off layer 21, can be used. However, in the case where the laser lift-off method is used, the laser light is reflected also by the layers which provide reflection layers at the periphery of the semiconductor layer 12 (the base layer 13 and the supporting portion outer peripheral portion 11a), thereby it being difficult to uniformly remove the lift-off layer in any place in the wafer. Therefore, in the case where such reflection layers are previously formed, it is preferable to use the above-described chemical lift-off method. Especially, in the case where the end portion of the semiconductor layer 12 has a taper angle, uniform lifting-off using the laser lift-off method is more difficult.
Further, in the above example, the case where GaN is used as the Group-III nitride semiconductor has been described, however, for the crystal structure related to the polarity, especially for the structure of the (000-1) N plane and the formation of the semi-polar plane, the same discussion can be applied to other Group-ITT nitride semiconductors, such as AlGaN and AlInGaN. Therefore, it is obvious that the structure and the manufacturing method as described above are also effective for these.
The above embodiment has been explained using a sapphire substrate or AlN template substrate as the growth substrate 20, however, as the growth substrate 20, substrates formed of any other materials, such as SiC and Si substrates, can be used, provided that, through the lift-off layer 21, and the like, good-quality group III nitride semiconductors, such as GaN, AlN, AlGaN, and BAlInGaN (for use as the n-type layer 11a, the luminescent layer 11b, and the p-type layer 11c) can be grown.
In the above example, the semiconductor layer 12 has been explained assuming that it is constituted by the n-type layer 12e, the luminescent layer 12a, and the p-type layer 12c each being formed of a GaN based material. However, even in other cases, it is obvious that the same effect is provided. For example, it is also obvious that a diode which utilizes a simple pn junction, or various semiconductor devices can be manufactured in the same manner. In the above example, the n-type layer and the p-type layer have been sequentially formed on the growth substrate, however, even if the order of the n-type layer and the p-type layer is inverted, the description is also true. In addition, the n-type layer and the p-type layer may not be formed of GaN, but of any other group III nitride semiconductor, for example, AlaInbGa1-a-bN (0≦a≦1, 0≦b≦1, and a+b≦1).
Hereinbelow, the result of actually manufacturing a light-emitting element chip having the above-mentioned configuration will be explained.
First, after forming the lift-off layer 21 (Cr and CrN as a result of nitriding the Cr, with a thickness of 18 nm) on the sapphire substrate (the growth substrate 20), the semiconductor layer 12 composed of the n-type layer 12e (n-type GaN, with a thickness of 7 μm), the InGaN MQW luminescent layer 12a (with a thickness of 0.1 μm), the p-type layer 12c (p-type GaN, with a thickness of 0.2 μm) was formed (the epitaxial growth step). Then, by the dry etching method, a part of the semiconductor layer 12 was removed to form separation grooves for separating the individual element regions of the p-type layer 12c, each being composed of a square of 1000 μm per side (the separation groove forming step). Here, the taper angle A of the end portion of the semiconductor layer 12 was specified to be 40° with the pitch between elements being specified to be 1250 μm. The formation of the separation grooves was performed by etching away the sapphire substrate by 0.2 μm, and confirming that the sapphire substrate was exposed. On the sapphire substrate surface which was exposed, a Cr layer which is thick enough to be able to cover the side face of the exposed lift-off layer 21 and a part of the n-type layer 12e (i.e., with a thickness of 400 nm) was formed by the lift-off method using a resist pattern (the separation groove filling step).
Over the entire surface in this configuration, the insulator layer 16 (SiO2, with a thickness of 350 nm) was formed, and a part of the insulator layer 16 on the Cr layer (the insulator layer opening 16a) and a part of the insulator layer 16 on the p-type layer 12c in the element region were removed with buffered hydrofluoric acid (BHF) (the insulator layer forming step). The insulator layer opening 16a was specified to be a portion having a width of 70 μm and a length of 900 μm in the central area of the separation groove which is located along each of the four sides of the element region. The insulator layer 16 on the p-type layer 12c was removed, except for that in the location opposed to the location of the auxiliary electrode 15b in the n-side electrode 15, thus 80% of the area of the p-type layer 12c having been exposed. Thereafter, on the exposed p-type layer 12c, the p-side electrode 14 (Ag, with a thickness of 0.2 μm) was formed (the first electrode forming step). At this time, a gap of 10 μm was provided between the p-side electrode 14 and the insulator layer 16 which is located at the periphery of the p-type layer 12c.
Further, the exposed filler 23 (the Cr layer) in the insulator layer opening 16a was covered with a photoresist, and a base layer 13 (Ni (100 nm)/Au (100 nm)/Cu (0.2 μm) was formed on the p-side electrode 14 and the insulator layer 16, and on the p-type layer 12c in the gap between these. Thereafter, by removing the photoresist, the base layer 13 in
Thereafter, on a part of the exposed Cr layer, a thick-film resist (the resist layer 100) having a width of 70 μm, a length of 900 μm, and a thickness of 100 μm was formed (the opening portion protection step).
Thereafter, using a copper sulfate based electrolyte and the base layer 13 as the seed, the supporting portion 11 formed of Cu having a thickness of 150 μm from the connection layer surface of the semiconductor layer was formed by electroplating (the supporting portion forming step). The supporting portion 11 is integrally formed over the entire area of the sapphire substrate.
Thereafter, using acetone, the thick-film resist was dissolved. Thereby, a hole or groove which penetrates from the surface of the supporting portion 11 to the filler 23 (the Cr layer) on the sapphire substrate was formed. Thereafter, by immersing the wafer in a Cr etchant with which Cr as well as CrN are selectively etched away, and through this thru-hole or groove, supplying the etchant to the Cr layer and the CrN layer 21 as the lift-off layer to dissolve the lift-off layer 21, the sapphire substrate 20 was peeled off (the lift-off step).
Thereafter, the n-type layer 12e of the lift-off surface was uniformly dry etched (the semiconductor layer etching step). By this etching, the n-type layer 12e was etched away from a thickness of 7 μm to a thickness of 5 μm. Further, by immersing the wafer in a KOH aqueous solution (6 mol/L) at 60° C. for 30 minutes, irregularities having a hexagonal pyramid-like shape with various sizes, the height from bottom to apex of the irregularities ranging from 0.4 to 1.5 μm, were formed on the surface (the irregularities forming step). In this case, the thickness of the n-type layer 12e from the uppermost point was specified to be 3.5 μm. Thereafter, the protection film 17 (SiO2) was deposited by 0.2 μm (the protection film forming step), and the protection film 17 in the place where the n-side electrode 15 is to be formed was removed by etching with BHF to expose the surface of the n-type layer 12e. On the surface of this n-type layer 12e having a surface in the hexagonal pyramid-like shape, the n-side electrode 15 (Ti/Ni/Au, with a thickness of 1.5 μm) having the auxiliary electrode 15b and the bonding pad part 15a corresponding to the pattern of the above-mentioned insulator layer 16 was formed (the second electrode forming step).
Finally, the difference in level between the surface of the n-type layer 12e (the apex of the hexagonal pyramid) and the surface of the top portion 11b of the supporting portion 11 made of Cu and having a concave geometry (exactly, the protection film surface) was approximately 2 μm (1.8 μm or over).
Using a flat collet, the assembly test was conducted on ten thousands pieces of the light-emitting element chip 10 in the present Example. The contact surface between the collet and the light-emitting element chip 10 is the supporting portion outer peripheral portion 11a, and since the collet will not be contacted with the surface of the n-side electrode 15 and the n-type layer 12e, no flaws and dents were generated on the surface of the upper electrode 15 and the n-type layer 12e.
Herein, as Comparative Example, a light-emitting element chip with a structure having no supporting portion outer peripheral portion 11a as that in Example was manufactured. This manufacture was performed by filling up all the separation grooves between semiconductor layers in the opening portion protection step with photoresist, and performing the other steps in the same manner.
In other words, in Comparative Example, there is provided the light-emitting element chip having a sectional structure shown in
Using a flat collet, the assembly test was conducted on ten thousand pieces of the light-emitting element chip 10 in this Comparative Example. As a result of the test, a flaw or chipping was observed in 151 pieces of the ten thousand pieces. In addition, a crack caused in the semiconductor layer was observed in 58 pieces of the ten thousand pieces. From the above-mentioned results, it has been verified that, in accordance with the present invention, no flaws or dents are produced in the n side electrode 15 (particularly in the auxiliary electrode 15b), and no impact is applied to the semiconductor layer at the time of assembly, whereby the assembly can be performed safely.
(Output Characteristics Example)
One thousand pieces of the light-emitting element in which the light-emitting element chip according to Example is assembled were caused to emit light by using a constant current power supply to feed a current of 350 mA. Around the light-emitting element chip, there is formed no structure, such as a reflection cup, or a plastic lens, which can have an effect on the luminous efficiency, except for the light-emitting element chip itself.
As described above, the taper angle θ for the semiconductor layer or the supporting portion outer peripheral portion can be controlled by adjusting the dry etching conditions in the separation groove forming step. In addition, this taper angle θ can have an effect on the efficiency of light taking-out.
The light-emitting element chip or the light-emitting element having the above-described configuration emits monochromatic light the color of which is determined by the material composition of the semiconductor layer 12. Contrarily to this, by forming a phosphor layer on the light-emitting face of the light-emitting element chip, light as a result of the light emitted by this phosphor layer being mixed with the light emitted by the semiconductor layer can be obtained. Here is a description about the case where, in order to obtain a pseudo white color, YAG emitting a yellow color is used as this phosphor on the light-emitting element emitting a blue color.
This phosphor layer is formed on the light-emitting face by baking it after being applied, however, it is required that the entire place of the semiconductor layer from which the emitted-light is taken out be covered with this phosphor layer.
On the other hand, in Comparative Example, as stated in, for example, Japanese Unexamined Patent Application Publication No. 2008-135539, it becomes necessary to form the phosphor layer 200 also at the side face. Therefore, the quantity of the phosphor material used was increased as compared to that in Example, being approximately three times the quantity required for that in Example. Further, in order to obtain uniform light emission, the thickness of the phosphor layer 200 is required to be uniform in all the places. However, in the case where the phosphor layer is to be formed both at the top face and the side face, it is difficult to provide a uniform thickness in all the places.
On the other hand, in Example, the light-emitting face has a structure in which the periphery thereof is raised as a bank, and only in the inside of this periphery, the phosphor layer 200 is needed to be formed, thereby it is easy to make the thickness of the phosphor layer 200 uniform within this bank like portion. Thereby, with the light-emitting element chip in Example, it is possible to suppress the increase in quantity of use of the expensive phosphor, and, in addition, to facilitate the control of the emitted-light color.
The configuration, geometry, size, and positional relationship which have been explained in the above embodiment are only those outlined to such an extent that the present invention can be understood and embodied, and in addition, the numerical values, the compositions of the respective components, and the like, are given only as exemplifications. Therefore, the present invention is not limited to the embodiment which has been explained, and can be modified to various embodiments within the scope of the technical concept as given in the claims.
The light-emitting element chip and the manufacturing method therefor in accordance with the present invention are applicable to LED optical system elements and methods for manufacturing the same.
Reference symbol 10 denotes a light-emitting element chip; 11 a supporting portion; 11a a supporting portion outer peripheral portion; 11b a top portion; 12 a semiconductor layer; 12a a luminescent layer; 12b a one face; 12c a p-type GaN layer (p-type semiconductor layer: p-type layer); 12d the other face; 12e an n-type GaN layer (n-type semiconductor layer: n-type layer); 13 a base layer; 14 a p-side electrode (one electrode); 15 an n-side electrode (the other electrode); 15a a bonding pad part (n-side electrode); 15b an auxiliary electrode (n-side electrode); 16 an insulator layer; 16a an insulator layer opening; 17 a protection film; 20 a growth substrate; 21 a lift-off layer; 23 a filler; 100 a resist layer (mask); and 200 a phosphor layer.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2011/002911 | 5/25/2011 | WO | 00 | 11/12/2013 |
