Claims
- 1. A method of synchronizing a clock signal to a data signal, comprising the steps of:(A) detecting a first edge of said data signal; (B) determining a first value indicating a position of said first edge; (C) adding said first value to a second value, wherein said second value indicates a position of a second edge of said data signal; and (D) adjusting said clock signal, based on the result of step (C), if said result is greater than a predetermined value.
- 2. The method of claim 1, further comprising the steps of:(E) detecting a third edge of said data signal; (F) determining a third value indicating a position of said third edge; (G) adding said third value to the result of step (c); and (H) adjusting said clock signal, based on the result of step (G), if said result of step (G) is greater than said predetermined value.
- 3. The method of claim 1, wherein step (D) further comprises:comparing the result of step (C) to a second predetermined value and adjust said clock signal only if the result is greater than said second predetermined value.
- 4. The method of claim 3, wherein step (D) further comprises:comparing the result of step (C) to a third predetermined value and adjust said clock signal only if the result is less than said third predetermined value.
- 5. The method of claim 1, wherein step (D) further comprises:comparing the result of step (C) to a second predetermined value; if said result is less than said second predetermined value, comparing the result to a third predetermined value; and adjusting said clock signal.
- 6. The method of claim 1, wherein step (D) further comprises selecting a number of clock phases based upon the result of step (C).
- 7. The method of claim 1, wherein step (D) further comprises:adjusting the result of step (C) in response to said first and second value when adding said first value and said second value would cause an overflow or underflow.
- 8. The method according to claim 1, wherein step (D) further comprises:incrementing or decrementing a counter value in order to adjust said clock signal.
- 9. The method of claim 1, wherein step (C) further comprises:storing said first value; and storing said second value.
- 10. The method according to claim 1, wherein step (D) further comprises:determining a phase offset magnitude.
- 11. The method according to claim 1, wherein step (D) further comprises:determining a magnitude of the result of step (C).
- 12. An apparatus comprising:means for detecting a first edge of said data signal; means for determining a first value indicating a position of said first edge; means for adding said first value to a second value, wherein said second value indicates a position of a second edge of said data signal; and means for adjusting said clock signal, based on the result of said means for adding, if said result is greater than a predetermined value.
- 13. An apparatus for synchronization of a clock signal to a data signal, comprising:a detector configured to detect a plurality of values, each indicating a position of an edge and adding said plurality of values to generate a result, wherein said detector is configured to adjust said clock signal, if said result is greater than a predetermined value.
- 14. The apparatus of claim 13, wherein the detector comprises an accumulator that adds a first value to a second value to produce said result.
- 15. The apparatus of claim 13, wherein the detector is further configured to compare said result to a second predetermined value and adjust said clock signal only if said result is greater than said second predetermined value.
- 16. The apparatus of claim 13, wherein the detector is further configured to compare said result to a third predetermined value and adjust said clock signal only if said result is less said third predetermined value.
- 17. The apparatus of claim 13, wherein the detector further comprises a register configured to store a value, a register configured to store said result, and an adder configured to add said result and said value.
- 18. The apparatus of claim 13, wherein said detector further comprises:a comparator configured to compare said result to said predetermined value; and a look ahead circuit configured to generate an enable signal in response to overflow or underflow condition.
- 19. The apparatus of claim 18, wherein said detector further comprises an increment/decrement logic circuit configured to adjust said result in response to a value and said enable signal.
- 20. The apparatus of claim 13, wherein said clock signal comprises a plurality of phases and said detector is configured to select one or said plurality of phases as system clock.
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 60/203,676, filed May 12, 2000 and is hereby incorporated by reference inits entirety.
The present application may relate to application Ser. No. 09/745,660, filed Dec. 21, 2000, Ser. No. 09/747,281, filed Dec. 21, 2000, Ser. No. 09/747,257, filed Dec. 22, 2000, Ser. No. 09/746,802, filed Dec. 22, 2000, and Ser. No. 09/747,188, filed Dec. 22, 2000, which are each hereby incorporated by reference in their entirety.
US Referenced Citations (21)
Non-Patent Literature Citations (5)
Entry |
Bertrand J. William et al., “Linearized Digital Phase-Locked Loop”, U.S. Ser. No. 09/745,660, Filed Dec. 21, 2000. |
Bertrand J. Williams et al., “Linearized Digital Phase-Locked Loop Method”, U.S. Ser. No. 09/747,281, Filed Dec. 21, 2000. |
Terry D. Little et al., “Linearized Digital Phase-Locked Loop”, U.S. Ser. No. 09/747,257, Filed Dec. 22, 2000. |
Timothy J. Jordan et al., “Linearized Digtal Phase-Locked Loop Method”, U.S. Ser. No. 09/747,188, Filed Dec. 22, 2000. |
Bertrand J. Williams et al., “Linearized Digital Phase-Locked Loop Method”, U.S. Ser. No. 09/746,802, filed Dec. 22, 2000. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/203676 |
May 2000 |
US |