1. Field
Embodiments of the disclosure relate generally to the field of photodiode control in detector systems and more particularly to embodiments for providing a capacitive transimpedance amplifier control circuit for linear response to a lower portion of the output swing and a logarithmic response to an upper portion of the output swing of the detector.
2. Background
A common circuit for use with photodiodes, such as visible, UV or IR and in quantities of one or millions, is the trans-impedance amplifier (TIA). This is also called a current-to-voltage converter. In the TIA circuit, a photodiode is connected to the input in such a way that the current from the diode flows in a feedback element that can be a resistor or a capacitor or combination. The current flow affects an output voltage change that is linear with light flux. The output voltage remains linear as long as the output of the amplifier is within its operating range. If the amplifier's output exceeds its output range (saturates), the output voltage can no longer move and no longer provides feedback and typically the bias voltage (the voltage across the diode) can no longer be maintained. If the photodiode were initially biased in a zero or near-zero (slightly reverse) bias, then this will become forward bias from lack of feedback and from continued flux on the photodiode detector. In previous circuits, this non-linear behavior made no difference to the output voltage. The saturated amplifier resulted in a “saturated” signal from too much flux.
The current-voltage relationship exhibited by a photodiode junction is given by:
where:
I=photodiode current
Isa=photodiode saturation current
q=electron charge
Vd=photodiode voltage
n=efficiency factor for photodiodes (n=1 for ideal diode and n=2 to 3 for real devices)
T=diode operating temperature
η=photodiode quantum efficiency
Qb=photodiode incident flux density
A=photodiode area
k=Boltzmann's constant
It is therefore desirable to provide a photo diode control circuit which avoids saturation to provide flexibility for high flux input to the photodiode detector.
Exemplary embodiments provide a dual mode amplifier circuit to receive output from a photodiode. In a first mode the amplifier portion of the circuit is in a linear range and the diode is operating in its current mode. In a second mode, the amplifier has saturated and as such no longer acts as an amplifier and the diode is allowed to self-bias into the voltage mode or log mode operation. In the first mode, the amplifier acts as a capacitive trans-impedance amplifier (CTIA) circuit with the photodiode providing a current input. An integration capacitor (feedback capacitor) is connected to receive the current and produces a voltage output. An input capacitor is also connected to receive the current input and drives an operational amplifier having an output connected to the voltage output node. For one exemplary embodiment, a correlated double-sample (CDS) capacitor is connected to the voltage output node. A sample and hold circuit incorporating a sample and hold capacitor samples the amplifier output. A log function on (LOGON) switch is connected between the operational amplifier output and the voltage output node and a reset switch connected to short the photodiode. The LOGON switch sequentially operates in conjunction with the reset switch at the end of an integration time allowing the integration capacitor to retain an integrated current (voltage) plus a log voltage with closing of the reset switch shorting the detector photodiode and offsetting the voltage on the integration capacitor into the negative voltage direction.
The exemplary embodiment provides a method for linear and logarithmic measurement of a diode detector by obtaining a current/voltage input from a diode detector which is then integrated/sampled on an integration capacitor and input through a capacitor to an operational amplifier. A double-sample capacitor is charged with an output from the operational amplifier and the integration capacitor. The output of the operational amplifier is interrupted after an integration period and the linear input from the integration capacitor is sampled for a first sample period. The diode detector is then shorted for sampling the logarithmic input voltage for a second sample period and a sample-and-hold circuit is activated to read the double-sample capacitor which now has the sum voltages of the linear mode and the log response. The amplifier and CDS capacitor are then reset for the next frame.
The features, functions, and advantages that have been discussed can be achieved independently in various embodiments of the present invention or may be combined in yet other embodiments further details of which can be seen with reference to the following description and drawings
For the case in which the photodiode current I is set to zero (i.e., the “open circuit” case), re-arrangement of this equation produces an expression for the “open circuit diode voltage” that indicates that this voltage will be proportional to the logarithm of input flux density:
Open circuit and “forward biased” (i.e., positive Vd regime) operation of the diode will produce a logarithmic voltage response of Vd to input flux density. A “reverse biased” (i.e., negative Vd regime) operation will produce a linear photodiode voltage response.
Referring to
The overall response of the circuit is such that out of the total output voltage range of the circuit (2.0 volts, for example), linear mode response is indicated in the 0.0°V to 1.5°V portion of the output swing. Logarithmic response is indicated in the 1.5V to 2.0V portion of the output swing. This significantly increases the dynamic range of the photodiode response. In an example of the CTIA embodiment, a good response might by 3½ orders of magnitude. Adding the log response, gives another 4 orders of magnitude, or more, albeit “compressed”. The output remains monotonic at all times and is automatic and instantaneous.
The following sections describe the detailed operation of the circuit in the five segments of its operation during a frame period. Timing relationships required to operate the circuit in automatic lin/log mode or in linear-only mode (dashed lines for RST and LOGON switches apply to linear-only mode) with control of the associated in-cell switches shown in
In a “RESET” segment 202, the starting configuration of the photodiode is established at the beginning of frame “n”. The respective switch states shown in
Next, in an INTEGRATE segment 204, with the switch states asserted as shown in
There are two sampling techniques. Sample Part A 206 is standard and does not use the LOGON switch 25 while Sample Part B 208 is the log mode and does use the LOGON switch 25.
To implement the standard mode, Sample Part A 206, at the end of integration time, the switches remain as shown in
For the Sample Part B 208 or log mode, at the end of the integration time, the Vout voltage will represent the integrated charge. As represented by
To implement sampling to measure the signal in Log Mode, the LOGON switch 25 is opened at the end of the integration time as shown in
In a READ segment 210, the signal voltage that is held on the output of the integration capacitor 20 (which is automatically transferred to the output of the CDS capacitor 26) is transferred to the sample-hold capacitor, Csh, 32 by closing the sample and hold switch, SH, 28. The signal voltage is thus transferred to the Csh capacitor. Alternatively, the SH could be held closed, during integration and thus the Csh capacitor would be allowed to charge during the entire integration time. With either technique, the SH switch is opened before the photodiode detector of the pixel is reset and the process repeats, thereby saving the signal voltage on the Csh capacitor.
Having now described various embodiments of the invention in detail as required by the patent statutes, those skilled in the art will recognize modifications and substitutions to the specific embodiments disclosed herein. Such modifications are within the scope and intent of the present invention as defined in the following claims.
This application claims priority of U.S. Provisional Application Ser. No. 61/368,441 filed on Jul. 28, 2010 entitled LINEAR/LOGARITHMIC CAPACITIVE TRANS-IMPEDANCE AMPLIFIER CIRCUIT the disclosure of which is incorporated herein by reference.
Number | Date | Country | |
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61368441 | Jul 2010 | US |