Patent Application
20140147593
The present invention relates generally to combinatorial methods for material development.
Sunlight control glasses are commonly used in applications such as building glass windows and vehicle windows, typically offering high visible transmission and low emissivity. High visible transmission can allow more sunlight to pass through the glass windows, thus being desirable in many window applications. Low emissivity can block infrared (IR) radiation to reduce undesirable interior heating.
In low emissivity glasses, IR radiation is mostly reflected with minimum absorption and emission, thus reducing the heat transferring to and from the low emissivity surface. Low emissivity, or low-e, panels are often formed by depositing a reflective layer (e.g., silver) onto a substrate, such as glass. The overall quality of the reflective layer, such as with respect to texturing and crystallographic orientation, is important for achieving the desired performance, such as high visible light transmission and low emissivity (i.e., high heat reflection). In order to provide adhesion, as well as protection, several other layers are typically formed both under and over the reflective layer. The various layers typically include dielectric layers, such as silicon nitride, tin oxide, and zinc oxide, to provide a barrier between the stack and both the substrate and the environment, as well as to act as optical fillers and function as anti-reflective coating layers to improve the optical characteristics of the panel.
The manufacture of low emissivity panels entails the integration and sequencing of many unit processing steps, with potential new process developments. For example, different combinations of infrared reflective layers and antireflective layers can exhibit different optical characteristics, affecting subsequent fabrication processes, and consequently the performance of the low emissivity structures. The precise sequencing and integration of the unit processing steps enables the formation of functional panels meeting desired performance metrics such as visible light transmission, infrared reflection, and reliability.
As part of the discovery, optimization and qualification of each unit process, it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices such as integrated circuits. In particular, there is a need to be able to test i) more than one material, ii) more than one processing condition, iii) more than one sequence of processing conditions, iv) more than one process sequence integration flow, and combinations thereof, collectively known as “combinatorial process sequence integration”, on a single monolithic substrate without the need of consuming the equivalent number of monolithic substrates per material(s), processing condition(s), sequence(s) of processing conditions, sequence(s) of processes, and combinations thereof. This can greatly improve both the speed and reduce the costs associated with the discovery, implementation, optimization, and qualification of material(s), process(es), and process integration sequence(s) required for manufacturing.
Systems and methods for High Productivity Combinatorial (HPC) processing are described in U.S. Pat. No. 7,544,574 filed on Feb. 10, 2006, U.S. Pat. No. 7,824,935 filed on Jul. 2, 2008, U.S. Pat. No. 7,871,928 filed on May 4, 2009, U.S. Pat. No. 7,902,063 filed on Feb. 10, 2006, and U.S. Pat. No. 7,947,531 filed on Aug. 28, 2009 which are all herein incorporated by reference. Systems and methods for HPC processing are further described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/419,174 filed on May 18, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/674,132 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005, and U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005 which are all herein incorporated by reference.
HPC processing techniques have been successfully adapted to wet chemical processing such as etching and cleaning. HPC processing techniques have also been successfully adapted to deposition processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD). However, HPC processing techniques have not been successfully adapted to the development of low emissivity panel characteristics, such as optical properties, to evaluate materials and process conditions for optimal low emissivity panel performance.
Therefore, there is a need to apply high productivity combinatorial techniques to the development and investigation of materials for the manufacture of clean energy devices and systems.
In some embodiments, methods and systems to control the temperature of a substrate during a deposition process, such as physical vapor deposition (PVD), are provided. A temperature controlled apertured shield can be disposed on the surface of the substrate, surrounding the substrate area that is subjected to the deposition process. The temperature controlled apertured shield can be actively cooled, for example, by a circulated coolant, which can absorb heat from the deposition region and maintain a desired temperature for the deposited films.
In some embodiments, systems and methods for regulating temperature of site isolated regions on a substrate are provided, allowing combinatorial deposition under controlled temperature. A site isolated region can be sealed using a temperature controlled apertured shield, which can be effective for regulating the temperature of the site isolated region, allowing a desired temperature for the deposition process.
In some embodiments, the temperature controlled apertured shield can be made from high thermal conductivity material, and can include inner channels for circulated coolant. By regulating the temperature of the coolant, for example, though a heat exchanger or a cooling mechanism, the apertured shield can be maintained at a desired temperature, leading to a desired temperature of the site isolated region, and preventing oxidation or hazing of the deposited films.
In some embodiments, the temperature controlled apertured shield can be used in a high productivity combinatorial (HPC) system. During normal operation of an HPC system, a reactor module including multiple reactors having temperature controlled apertured shields can create multiple site isolated regions on a substrate surface. The site isolated regions then can be processed with process conditions, device structures, or materials varying in a combinatorial manner.
In some embodiments, a reactor having a temperature controlled apertured shield can press on a region of the substrate surface to create a site isolated region. The temperature controlled apertured shield can regulate the temperature of the site isolated region to prevent degradation of the deposited film.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The drawings are not to scale and the relative dimensions of various elements in the drawings are depicted schematically and not necessarily to scale.
The techniques of the present invention can readily be understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
A detailed description of one or more embodiments is provided below along with accompanying figures. The detailed description is provided in connection with such embodiments, but is not limited to any particular example. The scope is limited only by the claims and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided for the purpose of example and the described techniques may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the embodiments has not been described in detail to avoid unnecessarily obscuring the description.
In some embodiments, combinatorial methods to deposit layers of material, including layers deposited by a physical vapor deposition (PVD) process, are disclosed. The methods can include cooling the substrate in the vicinity of the area to be deposited, for example, by using an apertured shield having circulated coolant. The methods can supplement the substrate cooling process, for example, by a substrate support, and can eliminate or reduce the heating of the substrate, for example, by the ion bombardment of the PVD process.
In the context of the present specification, an aperture shield can include a shielding plate that has one or more apertures. For example, the shielding plate can block materials, e.g., shielding materials from passing through. The apertures can allow materials to pass through the shield plate.
In some embodiments, the methods can utilize an apertured shield having channels within the apertured shield for a circulated fluid coolant. The apertured shield can include an opening for the materials to pass through the shield and be deposited on the substrate. The apertured shield can be placed on the substrate, and the substrate can be cooled by contact.
In the following description, illustrative methods and systems for substrate cooling during a deposition process are shown using simple schematic structures and process flows. Those skilled in the art will appreciate that the description and teachings to follow can be readily applied to any simple or complex testing methodology. The drawings are for illustrative purposes only and do not limit the application of the present invention.
“Combinatorial Processing” generally refers to techniques of differentially processing multiple regions of one or more substrates. Combinatorial processing generally varies materials, unit processes or process sequences across multiple regions on a substrate. The varied materials, unit processes, or process sequences can be evaluated (e.g., characterized) to determine whether further evaluation of certain process sequences is warranted or whether a particular solution is suitable for production or high volume manufacturing.
For example, thousands of materials are evaluated during a materials discovery stage, 102. Materials discovery stage, 102, is also known as a primary screening stage performed using primary screening techniques. Primary screening techniques may include dividing substrates into coupons and depositing materials using varied processes. The materials are then evaluated, and promising candidates are advanced to the secondary screen, or materials and process development stage, 104. Evaluation of the materials is performed using metrology tools such as electronic testers and imaging tools (i.e., microscopes).
The materials and process development stage, 104, may evaluate hundreds of materials (i.e., a magnitude smaller than the primary stage) and may focus on the processes used to deposit or develop those materials. Promising materials and processes are again selected, and advanced to the tertiary screen or process integration stage, 106, where tens of materials and/or processes and combinations are evaluated. The tertiary screen or process integration stage, 106, may focus on integrating the selected processes and materials with other processes and materials.
The most promising materials and processes from the tertiary screen are advanced to device qualification, 108. In device qualification, the materials and processes selected are evaluated for high volume manufacturing, which normally is conducted on full substrates within production tools, but need not be conducted in such a manner. The results are evaluated to determine the efficacy of the selected materials and processes. If successful, the use of the screened materials and processes can proceed to pilot manufacturing, 110.
The schematic diagram, 100, is an example of various techniques that may be used to evaluate and select materials and processes for the development of new materials and processes. The descriptions of primary, secondary, etc. screening and the various stages, 102-110, are arbitrary and the stages may overlap, occur out of sequence, be described and be performed in many other ways.
This application benefits from High Productivity Combinatorial (HPC) techniques described in U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007 which is hereby incorporated for reference in its entirety. Portions of the '137 application have been reproduced below to enhance the understanding of the present invention. The embodiments described herein enable the application of combinatorial techniques to process sequence integration in order to arrive at a globally optimal sequence of high-k device fabrication process with metal gate by considering interaction effects between the unit manufacturing operations, the process conditions used to effect such unit manufacturing operations, hardware details used during the processing, as well as materials characteristics of components utilized within the unit manufacturing operations. Rather than only considering a series of local optimums, i.e., where the best conditions and materials for each manufacturing unit operation is considered in isolation, the embodiments described below consider interactions effects introduced due to the multitude of processing operations that are performed and the order in which such multitude of processing operations are performed when fabricating a semiconductor device. A global optimum sequence order is therefore derived, and as part of this derivation, the unit processes, unit process parameters and materials used in the unit process operations of the optimum sequence order are also considered.
The embodiments described further analyze a portion or sub-set of the overall process sequence used to manufacture a semiconductor device. Once the subset of the process sequence is identified for analysis, combinatorial process sequence integration testing is performed to optimize the materials, unit processes, hardware details, and process sequence used to build that portion of the device or structure. During the processing of some embodiments described herein, structures are formed on the processed substrate which are equivalent to the structures formed during actual production of the high-k device. For example, such structures may include, but would not be limited to, high-k dielectric layers, metal gate layers, spacers, or any other series of layers or unit processes that create an intermediate structure found on semiconductor devices. While the combinatorial processing varies certain materials, unit processes, hardware details, or process sequences, the composition or thickness of the layers or structures or the action of the unit process, such as cleaning, surface preparation, deposition, surface treatment, etc. is substantially uniform through each discrete region. Furthermore, while different materials or unit processes may be used for corresponding layers or steps in the formation of a structure in different regions of the substrate during the combinatorial processing, the application of each layer or use of a given unit process is substantially consistent or uniform throughout the different regions in which it is intentionally applied. Thus, the processing is uniform within a region (inter-region uniformity) and between regions (intra-region uniformity), as desired. It should be noted that the process can be varied between regions, for example, where a thickness of a layer is varied or a material may be varied between the regions, etc., as desired by the design of the experiment.
The result is a series of regions on the substrate that contain structures or unit process sequences that have been uniformly applied within that region and, as applicable, across different regions. This process uniformity allows comparison of the properties within and across the different regions such that the variations in test results are due to the varied parameter (e.g., materials, unit processes, unit process parameters, hardware details, or process sequences) and not the lack of process uniformity. In the embodiments described herein, the positions of the discrete regions on the substrate can be defined as needed, but are preferably systematized for ease of tooling and design of experimentation. In addition, the number, variants and location of structures within each region are designed to enable valid statistical analysis of the test results within each region and across regions to be performed.
It should be appreciated that various other combinations of conventional and combinatorial processes can be included in the processing sequence with regard to
Under combinatorial processing operations the processing conditions at different regions can be controlled independently. Consequently, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, deposition order of process materials, process sequence steps, hardware details, etc., can be varied from region to region on the substrate. Thus, for example, when exploring materials, a processing material delivered to a first and second region can be the same or different. If the processing material delivered to the first region is the same as the processing material delivered to the second region, this processing material can be offered to the first and second regions on the substrate at different concentrations. In addition, the material can be deposited under different processing parameters. Parameters which can be varied include, but are not limited to, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, atmospheres in which the processes are conducted, an order in which materials are deposited, hardware details of the gas distribution assembly, etc. It should be appreciated that these process parameters are exemplary and not meant to be an exhaustive list as other process parameters commonly used in semiconductor manufacturing may be varied.
As mentioned above, within a region, the process conditions are substantially uniform, in contrast to gradient processing techniques which rely on the inherent non-uniformity of the material deposition. That is, the embodiments, described herein locally perform the processing in a conventional manner, e.g., substantially consistent and substantially uniform, while globally over the substrate, the materials, processes, and process sequences may vary. Thus, the testing will find optimums without interference from process variation differences between processes that are meant to be the same. It should be appreciated that a region may be adjacent to another region in one embodiment or the regions may be isolated and, therefore, non-overlapping. When the regions are adjacent, there may be a slight overlap wherein the materials or precise process interactions are not known, however, a portion of the regions, normally at least 50% or more of the area, is uniform and all testing occurs within that region. Further, the potential overlap is only allowed with material of processes that will not adversely affect the result of the tests. Both types of regions are referred to herein as regions or discrete regions.
In some embodiments, layers having different materials and/or process conditions are fabricated and tested to evaluate their characteristics and behaviors, for example, to identify their electrical conductivity, or their surface roughness.
In some embodiments, methods to deposit layers having different materials on a substrate are provided, including PVD processes. PVD processes can employ plasma ambient and ion bombardment for sputter materials from a target to be deposited on a substrate. The plasma ambient and ion bombardment can heat the substrate, and degrade the deposited layer characteristics.
In some embodiments, combinatorial workflows for evaluating material characteristics and behaviors using PVD processes are provided. High productivity combinatorial processing can be a fast and economical technique for screening materials to determine their proper process integration in advanced semiconductor devices.
Combinatorial processing can be used to produce and evaluate different materials, chemicals, processes, process and integration sequences, and techniques related to semiconductor fabrication. For example, combinatorial processing can be used to determine optimal processing parameters (e.g., power, time, reactant flow rates, temperature, etc.) of dry processing techniques such as dry etching (e.g., plasma etching, flux-based etching, reactive ion etching (RIE)) and dry deposition techniques (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.). Combinatorial processing can be used to determine optimal processing parameters (e.g., time, concentration, temperature, stirring rate, etc.) of wet processing techniques such as wet etching, wet cleaning, rinsing, and wet deposition techniques (e.g., electroplating, electroless deposition, chemical bath deposition, etc.).
In some embodiments, the dielectric layer is formed through a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The metal electrode layer can be formed by PVD, CVD or ALD through a shadow mask or by a lithography patterning process.
The process chamber provides a controlled atmosphere so that sputtering can be performed at any gas pressure or gas composition necessary to perform the desired combinatorial processing. Typical processing gases include argon, oxygen, hydrogen, or nitrogen. However, additional gases can be used as desired for particular applications.
The transport system can include a substrate support capable of controlling substrate temperature up to about 550 C, and applying a bias voltage of a few hundred volts.
In a sputter system 400, a plurality of sputtering sources 416 are positioned at an angle so that they can be aimed through a single apertured shield 414 to a site-isolated region on a substrate 406. The sputtering sources 416 are positioned about 100-300 mm from the apertured shield 414 to ensure uniform flux to the substrate within the site-isolated region. Details of the combinatorial PVD system are described in U.S. patent application Ser. No. 12/027,980 filed on Feb. 7, 2008 and U.S. patent application Ser. No. 12/028,643 filed on Feb. 8, 2008, which are herein incorporated by reference.
In some embodiments, a deposition process can be performed in the sputter system 400 in a combinatorial manner. The combinatorial deposition process generally includes exposing a first site-isolated region of a surface of a substrate to material from a sputtering source under a first set of process parameters, and exposing a second site-isolated region of a surface of the substrate to material from a sputtering source under a second set of process parameters. During exposure of the surface of the substrate to the sputtering source, the remaining area of the substrate is not exposed to the material from the sputtering target, enabling site-isolated deposition of sputtered material onto the substrate. The combinatorial process can further include exposing three or more site-isolated regions of the substrate to material from a sputtering source under distinct sets of process parameters. The combinatorial process can further comprise depositing additional layers onto any site-isolated region to build multi-layered structures if desired. In this manner, a plurality of process conditions to deposit one or a plurality of layers can be explored on a single substrate under distinct process parameters.
The process parameters that can be combinatorially varied generally comprise sputtering parameters, sputtering atmosphere parameters, substrate parameters, or combinations thereof. Sputtering parameters typically comprise exposure times, power, sputtering target material, target-to-substrate spacing, or a combination thereof. Sputtering atmosphere parameters typically comprise total pressure, carrier gas composition, carrier gas flow rate, reactive gas composition, reactive gas flow rate, or combinations thereof. The reactive gas flow rate can be set to greater than or equal to zero in order to vary the reactive gas composition in an inert carrier gas. The substrate parameters typically comprise substrate material, surface condition (e.g., roughness), substrate temperature, substrate bias, or combinations thereof.
Substrates can be a conventional round 200 mm, 300 mm, or any other larger or smaller substrate/wafer size. In other embodiments, substrates may be square, rectangular, or other shape. One skilled in the art will appreciate that substrate may be a blanket substrate, a coupon (e.g., partial wafer), or even a patterned substrate having predefined regions. In some embodiments, a substrate may have regions defined through the processing described herein.
Top chamber portion 518 of chamber 500 in
Shield 512 is capable of being moved in and out of chamber 500, i.e., the shield is a replaceable insert. Shield 512 includes an optional top portion, sidewalls and a base. In some embodiments, shield 512 is configured in a cylindrical shape, however, the shield may be any suitable shape and is not limited to a cylindrical shape.
The base of shield 512 includes a plurality of openings 514 in an aperture plate through which one or more site-isolated region of the surface of substrate 506 is exposed for deposition or some other suitable semiconductor processing operations. Aperture shutter 520 is moveably disposed over the base of shield 512. In some embodiments, aperture shutter 520 can be moved across a bottom surface of the base of shield 512 in order to cover or expose one or more openings 514. Typically, only one opening is uncovered at any one time to prevent cross-contamination between site-isolated regions. In some embodiments, aperture shutter 520 is controlled through an arm extension which moves the aperture shutter to expose or cover an opening 514. It should be noted that although a single opening per sputtering source is illustrated, multiple openings may be included for each sputtering source. Each opening can be associated with a dedicated aperture shutter or an aperture shutter can be configured to cover more than one opening simultaneously or separately. Alternatively, opening 514 can be a larger opening and aperture shutter 520 can extend with that opening to either completely cover the opening or place one or more fixed aperture shutters within that opening for processing the defined regions. The dual rotary substrate support 504 is useful to the site-isolating mechanism, and allows any location of the substrate or wafer to be placed under the opening 514. Hence, site-isolated deposition is possible at any location on the wafer/substrate.
A sputtering source shutter, 522 can also be included. Sputtering source shutter 522 functions to seal off a deposition source when the deposition source may not be used for the processing in some embodiments. For example, two sputtering sources 516 are illustrated in
Top chamber portion 518 of chamber 500 of
Low thermal conductivity substrates, such as glass panels, can be overheated due to the ion bombardment during long sputtered deposition period. Substrate cooling through the pedestal can be inadequate, especially for thick glass substrates. The high substrate temperature can potentially affect the quality of the deposited films, such as film oxidation or hazing.
In some embodiments, methods and systems to control the temperature of a substrate during a physical vapor deposition (PVD) process are provided. A temperature controlled apertured shield can be used to cool the substrate surface at the area surrounding the deposition area. The apertured shield can include a circulated fluid, e.g., coolant, which can maintain the apertured shield at a desired temperature, such as room temperature or below 100 C. The low temperature can improve the deposition characteristics, for example, to prove a silver layer with smooth surface and high conductivity for low emissivity glass panels. Alternatively, the circulated fluid can be used to heat the substrate.
In some embodiments, the temperature controlled apertured shield can be made from high thermal conductivity material, and can include inner channels for circulated coolant. By regulating the temperature of the coolant, for example, though a heat exchanger or a cooling mechanism, the apertured shield can be maintained at a desired temperature, leading to a desired temperature of the site isolated region, and preventing oxidation or hazing of the deposited films. By using a high thermal conductivity material, the temperature of the apertured shield can be uniform, and heat can be dissipated quickly by the circulated coolant. The apertured shield can be made from materials having thermal conductivity greater than that of glass, e.g., greater than about 0.1 W/(m·K). The apertured shield can be made from materials having thermal conductivity greater than about 1 W/(m·K).
Without the temperature controlled apertured shield, the substrate can heat up during the deposition process, for example, due to the ion bombardment from the target 640. In some embodiments, the temperature of the substrate can be controlled through a substrate support. The apertured shield can further regulate the substrate temperature, especially for low thermal conductivity substrates such as glass or ceramic. Since the apertured shield can regulate the temperature of the substrate top surface, e.g., the surface where the deposition occurs, the apertured shield can be used for various substrates, including substrates having low thermal conductivity property.
In some embodiments, the shield 770 can be placed on the substrate, with the opening 715 of the apertured shield defining a site isolated region. After the deposition, the shield 770 can be moved to another location, with the opening 715 of the apertured shield defining another site isolated region. The process can be repeated until the deposition process can be performed on all site isolated regions.
In
In
In some embodiments, methods and systems for combinatorially processing a substrate are provided. For example, in a first processing step, a first site isolated region of a substrate, defined by an apertured shield, is processed, for example, by depositing a layer. In a second processing step, sequentially executed after the first step, a second site isolated region of the substrate, contiguous (e.g., adjacent with or without overlapping) to the first region, is processed. The second site isolated region of the substrate is also defined by the apertured shield, which moves to process the second region. The first region and the second region may be adjacent to one another, or may be separated by a gap. The process parameters used to process the multiple site isolated regions, such as variations of materials, unit processes, and process sequences, can be varied in a combinatorial manner. The combinatorial process can provide a simple and cost effective screening of manufacturing operations to derive optimum manufacturing methods or integration sequences.
In
In some embodiments, a step-and-repeat method can be used to achieve multiple site isolated regions on a substrate using an apertured shield.
In
In some embodiments, combinatorial processes are disclosed in which site isolated regions are surrounded by a temperature controlled apertured shield. The temperature controlled apertured shield can provide additional cooling to the substrate, especially at the site isolated region being processed.
In some embodiments, a combinatorial reactor assembly having a temperature controlled apertured shield can press on a region of the substrate surface to create a site isolated region. The temperature controlled apertured shield can regulate the temperature of the site isolated region to prevent degradation of the deposited film.
In some embodiments, systems and methods for regulating temperature of site isolated regions on a substrate are provided, allowing combinatorial deposition under controlled temperature. A site isolated region can be sealed through a temperature controlled apertured shield, which can be effective for regulating the temperature of the site isolated region, allowing a desired temperature for the deposition process.
In some embodiments, the temperature controlled apertured shield can be used in a high productivity combinatorial (HPC) system. During normal operation of an HPC system, a reactor module including multiple reactors having temperature controlled apertured shields can create multiple site isolated regions on a substrate surface. The site isolated regions then can be processed with process conditions, device structure or materials varying in a combinatorial manner.
In some embodiments, a combinatorial processing chamber can be provided. The combinatorial processing chamber can include a substrate support and a combinatorial reactor assembly, wherein the substrate support is disposed under the combinatorial reactor assembly. The substrate support is configured to receive a substrate and can be coupled to a movement mechanism for rotating, horizontally translating or up/down movements. The combinatorial reactor assembly can include a PVD process mechanism, configured to sputter deposit a layer on one or more site isolated regions on the substrate. A temperature controlled apertured shield can be included to regulate the temperature of the substrate, such as the site isolated regions that are being processed.
A substrate can be introduced to the substrate support, for example, from a loading station, and through a robotic transfer mechanism. The substrate support can be raised up, to be coupled with the apertured shield of the combinatorial reactor assembly. One or more site isolated regions on the substrate can be processed using the combinatorial reactor assembly.
After completing processing, the substrate is lowered to be separated from the combinatorial reactor assembly, and then moved relative to the combinatorial reactor assembly. For example, the substrate or the substrate support can be rotated or translated while the combinatorial reactor assembly is stationary, so that the reactor assembly is positioned at different regions on the substrate surface. Alternatively, the combinatorial reactor assembly can be rotated or translated while the substrate is stationary. In some embodiments, the substrate is moved so that the reactor assembly can be positioned at second substrate surface regions between the first already-processed substrate surface regions. The process can continue, e.g., additional site isolated regions on the substrate can be processed using the combinatorial reactor assembly. The processing can be repeated, for example, until the whole substrate is processed. The apertured shield in the combinatorial reactor assembly can be configured so that the apertured shield can be adjacent or overlapping the site isolated regions that have been processed.
The combinatorial processing technique can be used to develop and investigate materials and processes for device processing and manufacturing. For example, in the combinatorial process, process parameters used to process the one or more regions are varied in a combinatorial manner. Alternatively, at least one region of the one or more regions is processed differently from at least one other region of the one or more regions. For example, different processing times can be used for different site isolated regions.
In some embodiments, multiple site isolation regions are processed on a substrate, with varying materials and process conditions for the different site isolated regions. In some embodiments, structural layers or patterned device structures can be fabricated, including lithographically defined active areas, and lithographically defined metal electrodes, aligned with the active areas.
In operation 1400, a substrate is provided. The substrate can include a glass or ceramic substrate, or a substrate that has low thermal conductivity, e.g., lower than that of a silicon substrate. The substrate can be positioned on a substrate support and under a combinatorial reactor assembly. A combinatorial process can be provided to form multiple site isolated regions on the substrate using the combinatorial reactor assembly. In operation 1410, the substrate is contacted by an apertured shield. The apertured shield can be a part of a process assembly, which can include a PVD process mechanism such as a target, power supply and gas sources. The apertured shield can include an opening, which can expose the substrate and form a site isolated region on the substrate. The apertured shield can be temperature controlled, for example, having an inlet and an outlet for a circulated coolant to regulate the temperature of the apertured shield.
In operation 1420, a layer can be deposited in the opening of the apertured shield. The layer can be deposited by a PVD process. In some embodiments, at least one characteristic of the deposited layer, or the PVD process that is used to deposit the layer, can be varied in a combinatorial manner between the site isolated regions. The characteristics can include the thickness of the PVD layer, the composition of the PVD layer, different targets for the PVD process, or different deposition conditions, e.g., deposition time or deposition temperature, of the PVD process. For example, a thickness of the PVD layer in one site isolated region can be 1 nm, and a thickness of the PVD layer in another site isolated region can be 2 nm.
The layer can include a coating for low emissivity panels, such as a protective layer, an oxide layer, a seed layer, or a reflective layer. The protective layer or barrier layer can include silicon nitride, silicon oxynitride, or other nitride material such as SiZrN, for example, to protect other layers from diffusion from the substrate. The oxide layer can include a metal or metal alloy oxide layer and can serve as an antireflective layer. The layer can include a seed layer for an infrared reflective film, for example, a zinc oxide layer deposited before the deposition of a silver reflective layer can provide a silver layer with lower resistivity, which can improve its reflective characteristics. The seed layer can comprise a metal such as titanium, zirconium, and/or hafnium, or a metal alloy such as zinc oxide, nickel oxide, nickel chrome oxide, nickel alloy oxides, chrome oxides, or chrome alloy oxides. The infrared reflective layer can be a metallic, reflective film, such as silver, gold, or copper.
The substrate can be moved relative to the combinatorial reactor assembly. Other site isolated regions on the substrate can continue to be processed using the combinatorial reactor assembly. The layers in multiple site isolated regions can be characterized according to each site isolated regions. The characterization can include structural characterization, such as interface bonding, amorphous layer or polycrystalline layer. The characterization can include optical or electrical characterization. The data related to the performance of the layers or devices can be extracted from the characterization. The optimum layers, including materials and process conditions can be selected based on a comparison of the layer performance.
In some embodiments, the method can further include circulating a gaseous or liquid coolant to the apertured shield, or maintaining the temperature of the apertured shield to be less than 100 C, including at room temperature, by the circulated coolant.
Although the foregoing examples have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed examples are illustrative and not restrictive.
