Patent Application
20060038765
This application claims the benefit of Korean Patent Application No. P2004-65414, filed on Aug. 19, 2004, which is hereby incorporated by reference in its entirety.
The invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device with a stabilized display.
Flat panel display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), electro-luminescent displays (ELDs), vacuum fluorescent displays (VFDs), etc. are frequently used as a display device. In particular, LCDs have replaced cathode ray tubes (CRTs) for use with mobile image display devices due to advantages such as superior picture quality, compact and lightweight structure, and low power consumption. Further, LCDs are used as TV monitors to receive and display broadcast signals and computer monitors such as laptop computers monitors.
An LCD device includes a liquid crystal panel for displaying an image and a drive circuit for applying drive signals to the liquid crystal panel. The liquid crystal panel includes a first and second glass substrates bonded to each other so as to have a certain space therebetween. A liquid crystal layer is injected between the first and second glass substrates.
The first glass substrate, which is also a thin film transistor (TFT) array substrate, includes a plurality of gate lines, a plurality of data lines, a plurality of pixel electrodes and a plurality of TFTs. Gate lines are arranged in one direction at certain regular intervals, and data lines are arranged in one direction perpendicular to the gate lines at certain regular intervals. Pixel electrodes are formed in a matrix pattern in pixel areas defined by the gate lines and the data lines. The TFTs are switched according to signals from the gate lines for transmitting signals from the data lines to the pixel electrodes.
In the second glass substrate, which is a color filter substrate, a light shield layer is formed to block incidence of light to a region other than the pixel areas. The second glass substrate includes R, G and B color filter layers for reproducing color tones and a common electrode for reproducing an image.
The LCD device operates based on optical anisotropy and polarization of liquid crystal. Since the liquid crystal has a thin and elongated molecular structure, the liquid crystal molecules have an orientation in a certain direction. It is possible to control the orientation of liquid crystal molecules by applying an electric field to the liquid crystal molecules.
The arrangement of liquid crystal molecules is controlled to change, so that the liquid crystal molecules exhibit optical anisotropy. Since light incident to the liquid crystal is refracted in the direction in which the liquid crystal molecules are oriented, image information is represented.
Currently, active matrix LCDs are often used because of superior moving picture reproduction. The active matrix LCDs include TFTs and pixel electrodes connected to the TFTs which are arranged in a matrix array.
Referring to
In the impulse-type operation mode of
In the sampling and holding operation mode of
For example, when an image, which is displayed in the above sampling and holding mode, is replaced with another image between two successive frame periods, an image signal corresponding to the next frame is applied to the concerned pixel under the condition that the image signal of the previous frame is not adequately discharged. As a result, a smooth data response with respect to each frame may not be provided.
The sampling and holding mode causing the motion blurring phenomenon is employed in a liquid crystal display device. The inherent viscosity and elasticity of the liquid crystal may result in a lower response speed and a certain period of holding time may need to be secured.
As shown in
To alleviate this motion blurring, a backlight blinking mode may be used. In
The intensity of the motion blurring is related to the length of holding time.
As shown in
When the LCD device operates at 60 Hz, one frame has a frame period of 16.67 ms (= 1/60 (sec)). The sampling and holding is carried out for 16.67 ms per frame. A liquid crystal panel having an XGA (1 024×768) resolution has 768 gate lines. In this case, the application time of a gate high voltage to each gate line (turn-on time of one line of TFT) corresponds to 21.7 μs (=16.67 ms/768).
The operation mode of
In the above high-speed operation, the sampling and holding time within one frame is very short, i.e., about half (½) time relative to a general operation mode. An adequate holding time may not be achieved. Because the voltage application time to each pixel electrode is cut in half, the data voltage to be applied is not adequately charged on the pixel electrode. As a result, brightness and image quality may be degraded.
Therefore, the LCD device of related art has several problems as follows. The LCD device has a lower response speed, as compared with other display devices, due to the inherent viscosity and elasticity of liquid crystal. During operation at a certain speed, a signal may be overlapped between two successive frames, thereby causing motion blurring.
To avoid this motion blurring, a backlight blinking method and a high-speed driving method are used. However, the backlight blinking method causes degradation in brightness and reduction in the service life of a backlight lamp, and the high-speed driving method may not obtain an adequate charging time. As a result, brightness may decrease and image quality may degrade. Accordingly, there is a need of an LCD device that substantially overcomes drawbacks of the related art.
By way of introduction only, in one embodiment, a liquid crystal display device comprises first and second substrates facing each other, a plurality of pairs of data lines, a plurality of gate lines, a plurality of pixel electrodes, a source driver, a gate driver and a latch circuit. The plurality of pairs of data lines are formed in a display section of the first substrate. Each of the pairs of data lines includes first and second data lines adjacent each other. The plurality of gate lines is formed on the first substrate so as to perpendicularly intersect the data lines. The gate lines define pixel areas between the first and second lines. The plurality of pixel electrodes is formed in each pixel area. The gate driver applies a gate signal to the gate lines and the source driver outputs data signals corresponding to the first and second data lines. The latch circuit stores a data signal output from a corresponding one of a plurality of output terminals of the source driver. The latch circuit also transmits relevant data signals to an odd pixel electrode and an even pixel electrode formed between the first and second data lines.
In other embodiment, a liquid crystal display device further comprises a plurality of first thin film transistors each formed at an intersection of the first data line and a corresponding odd one of the gate lines and electrically connected to a corresponding one of the pixel electrodes; a plurality of second thin film transistors each formed at an intersection of the second data line and a corresponding even one of the gate lines and electrically connected to a corresponding one of the pixel electrodes. The LCD device also comprise a first sampling/holding unit and a second sampling/holding unit each for storing a data signal operable to output from a corresponding one of a plurality of output terminals of the source driver.
In an LCD device, during a high-speed operation, a data signal from the source driver is bisected and then applied as an odd data signal and an even data signal to two neighboring data lines at certain time intervals. As a result, a charging time for the data signal may be secured and the data signal may be displayed in a stable manner.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) and together with the description serve to explain the principle of the invention. In the drawings:
Reference will now be made in detail to the preferred embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
The LCD device operates at a high speed of 120 Hz, and one frame has a frame period of 8.3 ms (= 1/120 s). The sampling time is twice as much as that of the high-speed operation mode of the related art, and the holding time is relatively shortened.
For example, a liquid crystal panel having an XGA (1 024×768) resolution has 768 gate lines. In a high-speed operation (120 Hz) of the related art, when a gate high signal is applied independently to each gate line, the gate on time (application time of gate high voltage) is 10.8 μs as noted above. In this LCD device, the gate on time for each gate line is extended to the level of 60 Hz operation. Thus, the application time of the gate high signal (gate on signal) to each gate line becomes 21.7 μs.
The average overlapped time between the neighboring lines is about half (½) period of the gate on time, i.e., 10.8 μs (=21.7 μs/2). The gate on time is extended twice, as compared with the high-speed operation of the related art. Thus, if the overlap period between neighboring gate lines is set at the half period of each gate on time, the gate lines placed on the panel may be sequentially turned on during a period of one frame. Therefore, in the LCD device, the gate on time (sampling time) is adequately secured so that the data voltage may be charged on the pixel electrode.
In the above overlap between gate lines, when the nth gate line is turned on (application of Vgn) in the first half gate on time, the gate line is turned on simultaneously with the (n−1)th gate line (application of Vg(n−1)), and in the second half gate on time, the gate line is turned on simultaneously with the (n+1)th gate line (application of Vg(n+1)).
When a gate on signal (gate high signal) is applied to the gate lines, it applies two neighboring gate lines. Unless the pixel structure is adjusted, it may occur that in the first half gate on time, a data voltage applied to a thin film transistor (TFT) associated with the (n−1)th gate line is applied to a TFT associated with the nth gate line, and in the second half gate on time, a data voltage applied to the TFT associated with the nth gate line is applied to a TFT associated with the (n+1)th gate line. In the overlap period of a gate high signal (the overlap period between Vgn and Vg(n−1) or the overlap period between Vgn and Vg(n+1)), if a data signal is applied simultaneously to TFTs associated with longitudinally neighboring gate lines, the pixel electrode may fail to charge an adequate data voltage. In this embodiment, the data signal may be applied to the TFTs at a different timing as will be described in conjunction with
As shown in
The LCD device 100 comprises a liquid crystal panel including the pixel part 20 and a pad part surrounding the pixel part. The LCD device 100 also comprises a gate driver (not shown) and the source driver 10 connected to the pad part of the liquid crystal panel. The pixel part 20 includes an array composed of a plurality of gate lines G1, G2, G3, . . . , and a plurality of pairs of data lines D1, D2, D3, D4, . . . ,.
Each output terminal DI1, . . . , DIN of the source driver 10 is connected to a first sampling/holding unit 11 and a second sampling/holding unit 12. The units 11 and 12 store a data signal from the output terminal DI1, . . . , DIN and transmit the stored data signal to a selected section. A first switch 19 transmits the data signal from the output terminal DI1, . . . , DIN selectively to the first sampling/holding unit 11 and the second sampling/holding unit 12. A second switch 13 applies the data signal stored in the first sampling/holding unit 11 selectively to a first data line D1. A third switch 14 applies the data signal stored in the second sampling/holding unit 12 selectively to a second data line D2. A first buffer 15 and a second buffer 16 are connected to the second switch 13 and the third switch 14 and apply the data signal to the first and second data lines D1 and D2 in a stable way.
The data signal is applied to a pixel electrode of each pixel area placed between the first and second data lines D1 and D2. The odd signal and the even signal from the source driver 10 alternately apply in synchronization with a gate high signal (Vgn) to a gate line associated with each pixel electrode. At this time, the first and second sampling/holding units 11 and 12 store the odd and even data signals and output them to the data lines. In other embodiment, the source driver 10 may include the first and second sampling/holding units 11 and 12, the first to third switches 19, 13 and 14, and the first and second buffers 15 and 16.
Although not illustrated, the output terminal of the gate driver is connected to the plurality of gate lines G1, G2, . . . , GM. Although only one output terminal DI1 of the source driver 10 is shown in
The gate driver applies a gate high signal to each gate line at 120 Hz, as shown in
In
As shown in
The pixel electrode 31 connected with the first thin film transistor 17 receives a data signal VD1 from the first data line D1. The pixel electrode 32 connected to the second thin film transistor 18 receives a data signal VD2 from the second data line D2. Here, the data signals supplied to the first and second data lines D1 and D2 are an odd signal and an even signal respectively, which are charged in different polarities when applied to the corresponding pixel electrodes. In this case, the data signals are applied to the first and second data lines D1 and D2 with a desired time difference (½ of the gate on time). At this time, the odd and even data voltages are stored and retained in the first and second sampling/holding units 11 and 12, and then applied to the pixel electrodes during the gate high signal period of the corresponding gate lines. As a result, data voltage values are adequately charged to drive the corresponding pixel electrodes.
In the LCD device 100, the signals from the source driver 10 are applied to a pair of data lines, i.e., first and second data lines D1 and D2 through the switching operations of the second and third switches 13 and 14. At this time, the data signal applied to the second data line D2 is delayed as long as the half period of the gate on time relative to the data signal applied to the first data line D1. These signals are applied to the pixel electrode in synchronization with a rising edge of the gate high signal.
Referring back to
In the LCD device 100, the gate high signal Vgn is applied to the gate lines, in such a manner that each gate on time of the previous gate line and the next gate line is overlapped with the current gate line during the first half period and the second half period, respectively. When the signal is applied to a gate line, an odd-mode data signal is applied to the first data line D1 through the second switch 13. After a half period of the gate on time, an even-mode data signal is applied to the second data line D2 through the third switch 14. For convenience of explanation, the first data line D1 and the output terminal DI1 are described. However, the LCD device 100 includes more first data lines and output terminals.
The first thin film transistors 17 are formed between the first data lines D1 and the odd gate lines G1 and the second thin film transistors 18 are formed between the second data lines D2 and the even gate lines G2. Even if the drive voltage is applied so as to be overlapped between neighboring gate lines G1, G2, . . . , GM during a half period of the gate on time, the thin film transistors 17 and 18 on the adjacent gate lines G1 and G2 are driven at different time points. In addition, the data signals are applied from the sampling/holding units 11 and 12, and not directly from the output terminal of the source driver 10. The data signals may be input in a stable and constant manner. It is possible to prevent degradations in pixel voltage and image quality which may result from the gate on time overlapping between neighboring gate lines. The first thin film transistors 17 and the second thin film transistors 18 may properly receive gate high signals in sequence, as if they operate at 60 Hz.
In the LCD device 100, even if the gate on time period is partially overlapped between neighboring gate lines, the odd-mode data signal and the even-mode data signal stored in the first and second sampling/holding units 11 and 12 are applied respectively to the first and second data lines. In synchronization with the rising edge of a gate high signal, a data signal is output during the gate high signal period. During the high signal overlap period between gate lines, an adequate sampling period is achieved such that a data voltage may be charged sufficiently on each individual pixel electrode. A data voltage having a stable gray scale value may be applied.
For the frame period of 8.3 ms (= 1/120 sec) of the high-speed operation at 120 Hz, a half period of the gate high signal is overlapped between the neighboring gate lines. Accordingly, the gate on time of each gate line corresponds to 21.7 μs (10.8 μs is overlapped between adjacent gate lines), but the data signal is applied so as not to overlap between neighboring gate lines. Therefore, an adequate gate on time is secured from the source driver such that the data voltage may be sufficiently charged and avoid the motion blurring phenomenon. The LCD device 100 is configured to drive the source driver 10 such that the odd-mode data signal and the even-mode data signal alternate at a period of one half of the gate high signal.
An image signal are supplied from the system to the first latch 22 of the source driver 10 and includes a 6-bit data signal each for R, G and B. For example, where the LCD device has an XGA resolution, the number of data lines in the liquid crystal panel is 1024×3×2, and the number of outputs of the source driver 10 is 1024×3. The number of outputs of the source driver 10 corresponds to one half of data lines provided in the liquid crystal panel. In
The operation of the source driver 10 with the above construction will be described below. The shift register 21 shifts the horizontal synchronous signal HSYNC in response to the source pulse clock signal HCLK and outputs the shifted signal as a latch clock to the first latch 22.
The first latch 22 samples and latches digital R, G and B data for each output terminal DI1, DI2, . . . , DIN in response to the latch clock output from the shift register 21. The second latch 23 receives and latches the R, G and B data latched by the first latch 22 simultaneously in response to a load signal LD.
The DAC 24 converts the digital R, G and B data latched by the second latch 23 into analog R, G and B data. The amplifier 25 operates to amplify the analog R, G and B data from the DAC 24 by a predetermined level and outputs the amplified data to each of the output terminals DI1, D12, . . . , DIN of the source driver of the panel.
The LCD device described above has various advantages and effects as follows. The liquid crystal panel may operate at a high speed, thereby significantly reducing the motion blurring phenomenon and improving the image quality.
The liquid crystal panel operates at a high speed and the gate on time is overlapped in a half period between neighboring gate lines. An adequate sampling time may be obtained for each gate line so as to charge a data voltage sufficiently on the pixel electrode. Therefore, brightness degradation may be prevented in the LCD device supplying a signal in a holding manner.
Although the liquid crystal panel operates internally at a high speed, the source driver is driven in a common way. Instead, each output terminal of the source driver is bisected and the bisected output terminal is connected to the sampling/holding unit. An adequate charging time may be provided to pixel electrodes when the data voltage is applied to the pixel electrodes. Thus, a high-speed operation may be achieved without newly constructing a high-cost source driver.
Each output terminal of the source driver is bisected such that the same data voltage is applied to neighboring data lines separately in an odd mode and an even mode at different time points. Thus, each pixel electrode corresponding to the data line is charged and driven separately at different time points so that a normal data voltage may be applied to each pixel electrode. As a result, image degradation and dim phenomenon may be prevented.
It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Thus, it is intended that the invention covers the modifications and variations provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2004-65414 | Aug 2004 | KR | national |
