Patent Grant
7312782
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2003-359733, filed on Oct. 20, 2003, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a liquid crystal display device having backlights.
2. Description of the Related Art
Liquid crystal display devices are in wide use for display devices of notebook personal computers and desktop personal computers since their power consumption is small and they require only small installation space. In recent years, liquid crystal display devices for television have been developed and are increasing their share of the market. Further, personal computers usable for viewing television broadcasting are being developed.
When they are used for television, improvement in display quality of moving images is especially demanded. As a method for improving display quality of moving images, a driving method of increasing response speed of liquid crystal, a method of on/off driving of backlights, and so on have been proposed. Devising on/off driving of backlights reduces blur of moving images occurring by so-called hold driving (disclosed in Japanese Unexamined Patent Application No. 2002-6815).
When the display system is a personal computer system, the control device is constituted of a control board mounted in a personal computer. This kind of control device has a function of converting image sources (video, DVD, television signals and so on) to signals with various resolutions and frequencies. The control device temporarily stores the image signal in a not-shown line memory or frame memory, so that it is capable of freely setting the output timing of the image signal and the control signal.
The timing controller starts turning on the backlights BL1 to BL4 in synchronization with the driving of predetermined horizontal lines (L1 to L4) so that lighting periods ON of the backlights BL1 to BL4 are equal to one another. Specifically, the timing controller asserts the backlight control signal BLCON1 low in synchronization with the driving of the horizontal line L1. Similarly, the timing controller asserts the backlight control signals BLCON2 to BLCON4 low in synchronization with the driving of the horizontal lines L1, L2, L3, respectively. The backlights BL1 to BL4 illuminate during low level periods of the backlight control signals BLCON1 to BLCON4 respectively.
The backlights BL1 to BL4 are turned off immediately before a subsequent frame image is displayed as described above. Specifically, the timing controller negates the backlight control signals BLCON1 to BLCON4 high in order to turn off the backlights BL1 to BL4 when the driven horizontal lines are 1, 193, 385, 577, respectively. Thus, the turning-on timing and turning-off timing of each of the backlights BL1 to BL4 are determined by the horizontal line numbers set in advance.
When the display system is a personal computer system, the output timings of the image signal and the control signal are generally changeable by the design of a personal computer manufacturer, users options, and so on. For example, when the output repetition rate of the image signal is to be made higher, the blank period BLANK becomes longer even with the same one frame period.
Further, the life of the backlights BL1 to BL4 depends on how long they illuminate. Therefore, the life of the backlights BL1, BL2 having longer lighting periods ON is shorter compared with the life of the backlights BL3, BL4 having shorter lighting periods ON. The backlights BL1 to BL4 are not replaceable individually since they are integrally structured as the backlight unit. Therefore, if any one of the backlights BL1 to BL4 is of no use, the entire backlight unit needs to be replaced. This means that the life of the backlight unit depends on the backlight having a longer lighting period ON, and the longer the period, the shorter the life. Further, brightness of the backlights BL1 to BL4 while they are on slightly lowers depending on the length of the lighting period ON thereof. Therefore, if the backlights BL1 to BL4 have different lighting periods ON, brightness of the backlights BL1 to BL4 while they are on will be differentiated through the long-term use.
The transition periods TP1, TP2 are characteristics peculiar to the backlight BL and they are constant irrespective of a refresh rate signifying one frame period and. Therefore, when the refresh rate is higher, a ratio of a stable period SP to a low level period (ON period in the drawing) of the backlight control signal BLCON is relatively low. In other words, even when the sum of the low level periods of the backlight control signal BLCON in a predetermined period is independent from the refresh rate and is constant, the brightness of the backlight BL (an integral value of the waveform in the drawing) is lower as the refresh rate is higher. As a result, for example, if a user of a personal computer manually sets a higher refresh rate, a screen of the liquid crystal display device becomes darker.
Further, a liquid crystal display device adopting a technique of on/off driving the backlights BL has a problem that the on/off period appears as flicker. The flicker is not conspicuous when an image in various colors displayed. But when an image with small motion is displayed (such as a case where a single color images over a plurality of frames is displayed on a part of a screen, the flicker is conspicuous.
It is an object of the present invention to prevent a change in brightness of a backlight of a liquid crystal display device even when a blank period changes.
It is another object of the present invention to prevent occurrence of a difference in brightness of a plurality of backlights of a liquid crystal display device even when a blank period changes.
It is still another object of the present invention to prevent a change in brightness of a backlight of a liquid crystal display device and to reduce flicker.
According to one of the aspects of the liquid crystal display device of the present invention, the liquid crystal display device has a liquid crystal panel in which a liquid crystal cell is arranged at intersecting areas of scanning lines and data lines. A plurality of backlights are disposed to face the liquid crystal panel and arranged in line in a wiring direction of the data lines. An image signal and a synchronous signal for generation of driving timings for the scanning lines and the data lines are supplied via external terminals respectively. A backlight driving circuit is controlled by a timing controller and execute on/off control of the backlights. The timing controller detects, using the synchronous signal, change in a blank period which is of one frame period for display of one screen and during which the image signal is not transmitted. Upon detecting the change in the blank period, the timing controller adjusts on-periods of the backlights in order to make brightness of the backlights equal to one another. Consequently, the backlights have equal brightness with one other in spite of the change in the blank period. This makes the lives of the backlights equal to one another. In a case where the plural backlights constitute a backlight unit, it is able to prevent reduction in life of the backlight unit. Further, it is also possible to prevent brightness of the backlights from being differentiated even through a long-term use.
According to another aspect of the liquid crystal display device of the present invention, the timing controller has a blank-line detecting unit and a timing calculating unit. The blank-line detecting unit finds the number of blank lines corresponding to the blank period, the number of blank lines being represented by the number of horizontal periods that are generation periods for the synchronous signal. The timing calculating unit finds the number of frame lines corresponding to one frame period by adding the number of blank lines to the number of horizontal lines that is the number of scanning lines, thereby setting a turning-on timing and turning-off timing of each of the backlights to serial numbers assigned to the frame lines. This can reduce the maximum value of the serial numbers which the blank-line detecting unit and the timing calculating unit handle. As a result, downsizing of, for example, a counter and so on and reduction in circuit scale of the timing controller are made possible. Further, it is able to reduce power consumption of the timing controller.
According to another aspect of the liquid crystal display device of the present invention, the timing controller has a blank dividing unit. The blank dividing unit divides the number of blank lines by the number of backlights to find the number of divided blank lines that is the number of blank lines per one backlight. The on-period of each of the backlights is represented by the number of illuminating frame lines that is a difference between the serial numbers indicating the turning-off timing and the turning-on timing, respectively. The timing calculating unit sets the number of illuminating frame lines to a sum of a preset number of lines and the number of divided blank lines. Dividing the blank period by the number of backlights and allotting the divided periods tp the respective on-periods of the backlights makes it possible to keep constant a ratio of the on-period to one frame period even when the blank period changes. If one frame period does not change, the on-period is constant, so that change in brightness due to the change in the blank period can be eliminated. For example, if there is a remainder after the division of the blank period by the number of backlights, the remainder is rounded off or rounded up, which can reduce circuit scale.
According to another aspect of the liquid crystal display device of the present invention, an external clock signal for putting the timing controller into operation is supplied via an external terminal. The timing controller has an image detecting unit, a blank-clock detecting unit, and a timing calculating unit. The image detecting unit finds the length of an image period which is of one frame period and during which the image signal is transmitted, as the number of clocks of the external clock signal. The blank-clock detecting unit finds the length of the blank period as the number of clocks of the external clock signal. The timing calculating unit adds the number of clocks counted by the blank-clock detecting unit to the number of clocks counted by the image detecting unit to find the number of frame clocks corresponding to one frame period, thereby setting a turning-on timing and a turning-off timing of each of the backlights by using serial numbers assigned to the frame clocks. Setting the turning-on timing and the turning-off timing using the numbers of the clocks of the external clock signal enables precise adjustment of the on-periods of the backlights.
According to another aspect of the liquid crystal display device of the present invention, the liquid crystal display device has an oscillator which generates an internal clock signal. The timing controller has an image detecting unit, a blank-clock detecting unit, and a timing calculating unit. The image detecting unit finds the length of an image period during which is of one frame period and during which the image signal is transmitted, as the number of clocks of the internal clock signal. The blank-clock detecting unit finds the length of the blank period as the number of clocks of the internal clock signal. The timing calculating unit adds the number of clocks counted by the blank-clock detecting unit to the number of clocks counted by the image detecting unit to find the number of frame clocks corresponding to one frame period, thereby setting a turning-on timing and a turning-off timing of each of the backlights by using serial numbers assigned to the frame clocks. Setting the turning-on timing and the turning-off timing using the number of clocks of the internal clock signal, makes it possible to keep constant the on-periods of the backlights corresponding to the number of clocks. As a result, the backlights can have constant brightness when not only the blank period but also the frame period change. For example, setting the frequency of the internal clock signal to a value lower than that of the external clock makes it possible to relatively reduce circuit scale of the timing controller, resulting in relative reduction in the power consumption.
According to another aspect of the liquid crystal display device of the present invention, a frequency divider divides a frequency of an external clock signal supplied via an external terminal to generate an internal clock signal. The timing controller has an image detecting unit, a blank-clock detecting unit, and a timing calculating unit. The image detecting unit finds the length of an image period which is of one frame period and during which the image signal is transmitted, as the number of clocks of the internal clock signal. The blank-clock detecting unit finds the length of the blank period as the number of clocks of the internal clock signal. The timing calculating unit adds the number of clocks counted by the blank-clock detecting unit to the number of clocks counted by the image detecting unit to find the number of frame clocks corresponding to one frame period, thereby setting a turning-on timing and a turning-off timing of each of the backlights using serial numbers assigned to the frame clocks. Setting the turning-on timing and the turning-off timing using the number of clocks of the internal clock signal that is generated by dividing the frequency of the external clock signal makes it possible to relatively reduce circuit scale of the timing controller, resulting in relative reduction in the power consumption compared with a case where an external clock signal is used.
According to another aspect of the liquid crystal display device of the present invention, the timing calculating unit sets the turning-off timings of the backlights so that in respective display areas of the liquid crystal panel corresponding to the backlights, brightness of the backlights lowers to an off-level brightness before display of an image signal of a subsequent frame is started. Consequently, it is possible to prevent appearance of an image of a subsequent frame while the backlights are on for display of an image of a certain frame. Therefore, it is able to prevent a moving image and so on from blurring.
According to another aspect of the liquid crystal display device of the present invention, a frame-head detecting unit outputs a detecting signal when detecting a head of each frame. One of the backlights corresponding to a head horizontal line is turned off in synchronization with an earlier timing between the turning-off timing found by the timing calculating unit and an output timing of the detecting signal. Consequently, the backlight can be surely turned off by the detecting signal even when one frame period is so short that there is no serial line needed for turning off the backlights. This can prevent a single backlight corresponding to the head horizontal line from continuously illuminating during one frame period. In other words, it is able to prevent brightness of the backlights from becoming different from one another.
(24, 25) According to another aspect of the liquid crystal display device of the present invention, an image analyzing unit outputs a flicker preventing signal when an image formed of image signals of a plurality of frames is in small motion. Alternatively, the flicker preventing signal is supplied via an external terminal. A backlight driving circuit stops the on/off control in response to the output of the flicker preventing signal so that the backlights continuously illuminates with predetermined brightness. For display of a slightly moving image in which flicker is conspicuous, the on/off control is stopped so as to keep the backlights illuminating with predetermined brightness, so that the occurrence of the flicker is made preventable.
The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The double circles in the drawings represent external terminals. In the drawings, each signal line shown by the heavy line is constituted of a plurality of lines.
Further, part of a block to which the heavy line is connected is constituted of a plurality of circuits. The same reference numerals and symbols as those of the external terminals are used to designate signals supplied via the external terminals. The same reference numerals and symbols as those of the signals are used to designate signal lines through which the signals are transmitted.
The timing controller 10 receives via the external terminals a clock signal CLK (external clock signal=dot clock signal), a data signal DATA0 (image signal), and an enable signal ENAB (synchronous signal) respectively to output a gate clock signal GCLK to the gate driver 12, a latch pulse signal LP and a data signal (image signal) DATA to the source driver 14, and backlight control signals BLCONS1 to BLCONS4 to the backlight driving circuit 20. The clock signal CLK functions as a basic clock signal for putting the timing controller 10 into operation. The enable signal ENAB is a synchronous signal for dividing the data signal DATA0 for each horizontal line as will be described later. The gate clock signal GCLK and the latch pulse signal LP are generated in synchronization with the enable signal ENAB. The data signal DATA has the same information as that of the data signal DATA0. The backlight control signals BLCON1 to BLCON4 are signals for turning on and off the backlights BL1 to BL4 respectively. The timing controller 10 will be explained in
The liquid crystal panel 16 has liquid crystal cells C formed at intersecting areas of the scanning lines G1 to Gn and the data lines D1 to Dm respectively. Each of the liquid crystal cells C is constituted of a thin film transistor TFT, a pixel electrode PE, and a not-shown liquid crystal and counter electrode. A gate of each of the thin film transistors TFT is connected to one of the scanning lines G1 to Gn, a drain thereof is connected to one of the data lines D1 to Dm, and a source thereof is connected to the pixel electrode PE. The counter electrode is disposed to face the pixel electrode PE. Further, liquid crystal is sandwiched by the pixel electrode PE and the counter electrode to constitute the liquid crystal cell C. The number of the scanning lines is 768 (n=768) in this embodiment. The liquid crystal cells C arranged along the scanning lines G1 to Gn constitute 768 horizontal lines.
The backlight unit 18 is constituted of the four backlights BL1 to BL4 arranged in line in the wiring direction of the data lines D1 to Dm and is disposed on a rear face of the liquid crystal panel 16 to face the liquid crystal panel 16. Each of the backlights BL1 to BL4 is constituted of, for example, a not-shown fluorescent tube and optical waveguide. Each of the backlights BL1 to BL4 is disposed for every 192 horizontal lines in the liquid crystal panel 16.
The backlight driving circuit 20 is constituted of an inverter for driving the fluorescent tubes. The backlight control circuit 20 outputs driving signals for turning on or off the fluorescent tubes of the backlights BL1 to BL4, in response to the backlight control signals BLCON1 to BLCON4 outputted from the timing controller 10. Note that, in this embodiment, the backlight driving circuit 20 turns on each of the fluorescent tubes with the maximum brightness when the logic level of each of the backlight control signals BLCON1 to BLCON4 indicates turn-on (low level), and lights each of the fluorescent tubes with 5% brightness (low brightness) of the maximum brightness when the logic level of each of the backlight control signals BLCON1 to BLCON4 indicates turn-off (high level). The fluorescent tubes are kept on with low brightness while the backlights BL1 to BL4 are off, so that they can be turned on next with quick increase in brightness. Therefore, the aforementioned transition period TP1 shown in
The line-clock detecting unit 22 finds the length of a generation period (pulse interval) of the enable signal ENAB using the number of clocks (the number of pulses) of the clock signal CLK. Specifically, the line-clock detecting unit 22 counts the number of the clocks in one horizontal line period (generation period of the enable signal ENAB), and outputs a line-clock signal LCLK indicating the found number of the clocks. The line-clock signal LCLK indicates the counted number of the clocks in binary number.
Note that the line-clock detecting unit 22 may count the number of the clocks of each of the plural horizontal line periods, find the average number of the clocks using only the number of the clocks existing in a predetermined range, and output the line-clock signal LCLK indicating the found number of the clocks. In this case, if the number of the clocks is not normal due to noises and so on, it will be excluded so that abrupt change in brightness of the backlights BL1 to BL4 can be prevented.
The blank-clock detecting unit 24 finds the length of a blank period BLANK in one frame as the number of clocks of the clock signal CLK. The blank period BLANK is a period which is of one frame period and during which an image signal is not transmitted, and is a period up to the start of a subsequent frame from the output of all the data signals DATA for one frame. For example, the blank period BLANK is detected when the pulse of the enable signal ENAB does not occur for a predetermined length of period or longer. The blank-clock detecting unit 24 outputs the found number of the clocks as a blank-clock signal BCLK. The blank-clock signal BCLK shows the found number of the clocks as a binary number.
The blank-line detecting unit 26 divides the number of the clocks (BCLK) indicated by the blank-clock signal BCLK by the number of the clocks (LCLK) indicated by the line-clock signal (LCLK) to find the number of horizontal lines (the number of blank lines) corresponding to the blank period BLANK, and outputs the found number of the horizontal lines as a blank-line signal BLN. Therefore, a clock-number ratio BCLK/LCLK is set as the number of the blank lines. The blank-line signal BLN shows the number of the blank lines as a binary number.
The ON/OFF timing calculating unit 28 receives the blank-line signal BLN to calculate the turning-on timing and the turning-off timing of each of the backlights BL1 to BL4. Specifically, the ON/OFF timing calculating unit 28 first adds the number of the blank lines to the number the horizontal lines that is the number of the scanning lines G1 to G768 to calculate the number of horizontal lines (the number of frame lines) corresponding to one frame period. The found frame lines are assigned line numbers (serial numbers) starting from “1” in sequence. The number of the scanning lines G1 to G768 of the liquid crystal panel 16 is a proper value of the liquid crystal panel 16. Therefore, the number of the frame lines is a value equal to the sum of 768 lines and the number of the blank lines indicated by the blank-line signal BLN. For example, when the blank-line signal BLN indicates 32 lines, one frame period corresponds to 800 lines.
In this embodiment, the ON/OFF timing calculating unit 28 sets the lighting period ON of each of the backlights BL1 to BL4 to 192 lines in advance. Therefore, the ON/OFF timing calculating unit 28 allots 192 lines to the lighting period ON out of the number of the horizontal lines (for example, 800 lines) of one frame period. This means that the difference between the line numbers for turning off and on each of the backlights BL1 to BL4 is always kept constant. Then, the ON/OFF timing calculating unit 28 calculates the line numbers for turning on and off each of the backlights BL1 to BL4 to output the calculated values as line signals LINE for the respective backlights BL1 to BL4.
The BLCON generating unit 30 counts the enable signals ENAB to find the horizontal line number. When the found horizontal number matches the line signal LINE, the BLCON generating unit 30 makes the corresponding one of the backlight control signals BLCON1 to BLCON4 fall or rise in order to turn on or off the corresponding one of the backlights BL1 to BL4.
Specifically, the ON/OFF timing calculating unit 28 judges that one frame period corresponds to 896 lines (768+128) to calculate the horizontal line numbers for turning on and off the backlights BL1 to BL4. The lighting period ON of each of the backlights BL1 to BL4 is set to 192 lines in advance. Therefore, the horizontal line numbers signifying the turning-on timings and the turning-off timings of the backlights BL1 to BL4 (“on lines, off lines”) are “705, 1”, “1, 193”, “193, 385”, and “385, 577” respectively. Even when the blank period BLANK is thus changed by the control from an external part of the liquid crystal display device, the lighting period ON of each of the backlights BL1 to BL4 is constantly set to 192 lines. Therefore, difference in brightness of the backlights BL1 to BL4 is prevented even when the blank period BLANK is changed.
In the first embodiment described above, by the adjustment of the lighting period ON of each of the backlights BL1 to BL4 according to the change in the blank period BLANK, the backlights BL1 to BL4 can have the same brightness regardless of the change in the blank period BLANK. As a result, the backlights BL1 to BL4 can have the same length of life, so that the reduction in the life of the backlight unit 18 can be prevented. Even the long-term use of the backlight unit 18 does not cause difference in brightness of the backlights BL1 to BL4.
The turning-on timing and the turning-off timing of each of the backlights BL1 to BL4 are set by the horizontal line numbers, so that the maximum value of the serial number dealt by the timing controller 10 can be made small. Accordingly, a counter and so on formed in the timing controller 10 can be downsized, resulting in the less number of wirings of signal lines. As a result, circuit scale of the timing controller 10 can be reduced to reduce power consumption of the timing controller 10.
The timing controller has an ON/OFF timing calculating unit 28A in place of the ON/OFF timing calculating unit 28 of the timing controller 10 (
The ENABI generating unit 32A outputs an internal enable signal ENABI synchronizing with an enable signal ENAB. The ENABI generating unit 32A generates the pulse of the internal enable signal ENABI at a same generation cycle as that of the pulse of the enable signal ENAB also in a blank period BLANK. The blank dividing unit 34A receives a blank-line signal BLN indicating the number of horizontal lines corresponding to the blank period BLANK, and in order to equally allot the blank period BLANK to lighting periods ON of respective backlights BL1 to BL4, it divides the number of the horizontal lines indicated by the blank-line signal BLN by “4” that is the number of the backlights BL1 to BL4 to output the division result as a 16-bit dividing signal DIV. Therefore, the dividing signal DIV indicates the number of divided blank lines that is the number of blank lines per one backlight.
The ON/OFF timing calculating unit 28A receives the blank-line signal BLN and the dividing signal DIV to calculate, as in the first embodiment, line numbers (serial numbers) signifying the turning-on timing and the turning-off timing of each of the backlights BL1 to BL4 respectively. Note that the ON/OFF timing calculating unit 28A sets the lighting period of each of the backlights BL1 to BL4 to the number of lines (the number of illuminating frame lines) equal to the sum of an initial value of 192 lines and the number of the divided blank lines indicated by the dividing signal DIV. Specifically, when the blank period BLANK corresponds to 32 lines and one frame period corresponds to 800 lines (768+32), the number of the illuminating frame lines corresponding to the lighting period ON of each of the backlights BL1 to BL4 is set to 200 lines (192+32/4). When the blank period BLANK corresponds to 128 lines and one frame period corresponds to 896 lines (768+128), the number of the illuminating frame lines is set to 224 lines (192+128/4). Then, the ON/OFF timing calculating unit 28A calculates the horizontal line numbers at which each of the backlights BL1 to BL4 is turned on and off to output the calculated values as a line signal LINE for each of the backlights BL1 to BL4.
In the above-described manner, the lighting period ON of each of the backlights BL1 to BL4 is constantly set to 25% of one frame period in this embodiment. As a result, the lighting period ON of each of the backlights BL1 to BL4 is prevented from changing even when the blank period BLANK changes, so that change in brightness of the backlights BL1 to BL4 is prevented.
The same effects as those of the first embodiment described above are also obtainable in this embodiment. Further, in this embodiment, the number of the horizontal lines signifying the blank period BLANK is quartered to be included in the lighting periods ON of the backlights BL1 to BL4, so that the ratio of the lighting period ON to one frame period can be always made constant even when the blank period BLANK changes. If one frame period is the same, the lighting period ON is constant. In this case, change in brightness due to the change in the blank period BLANK can be eliminated.
The timing controller has a blank dividing unit 34B in place of the blank dividing unit 34A of the timing controller of the second embodiment. The other configuration is substantially the same as that of the timing controller of the second embodiment. In addition to the function of the blank dividing unit 34A of the second embodiment, the blank dividing unit 34B has a rounding-off function when the number of horizontal lines indicated by a blank-line signal BLN is not dividable by 4. The rounding-off can minimize the load on an ON/OFF timing calculating unit 28A and simplify circuitry. The simplified circuitry makes it possible to reduce power consumption while the timing controller is in operation.
When the blank period BLANK changes from the state shown in
The same effects as those of the first and second embodiments described above are also obtainable in this embodiment. Further, owing to the rounding-off process at the time when the horizontal lines of the blank period BLANK are allotted to the backlights BL1 to BL4, it is possible to reduce load on the circuits and simplify circuitry. Moreover, power consumption while the timing controller is in operation can be reduced.
The timing controller has an image detecting unit 36C, an ON/OFF timing calculating unit 28C, and a BLCON generating unit 30C in place of the line-clock detecting unit 22, the ON/OFF timing calculating unit 28, and the BLCON generating unit 30 of the timing controller (
The image detecting unit 36C receives an enable signal ENAB and a clock signal CLK, to find a period (an image period) which is of one frame period, and during which a data signal DATA (an image signal) is transferred, using the number of clocks (the number of pulses) of the clock signal CLK. In other words, the number of the clocks of the image period is counted. The image detecting unit 36C outputs the found number of the clocks as an image clock signal PCLK. The image clock signal PCLK shows the found number of the clocks as a binary number.
The ON/OFF timing calculating unit 28C receives the image clock signal PCLK and a blank clock signal BCLK to calculate the turning-on timing and the turning-off timing of each of backlights BL1 to BL4.
Specifically, the ON/OFF timing calculating unit 28C first adds the number of the clocks indicated by the image clock signal PCLK and that indicated by the blank clock signal BCLK to find the number of clocks corresponding to one frame period. Next, the ON/OFF timing calculating unit 28C calculates clock numbers at which each of the backlights BL1 to BL4 turned on and off respectively to output the calculated values for each of the backlights BL1 to BL4 as a clock number signal NCLK. Here, the clock number (serial number) is assigned in each frame from “1” in sequence. Note that a lighting period ON of each of the backlights BL1 to BL4 is set as a fixed number of clocks in advance.
The BLCON generating unit 30C counts the clock signals CLK, and when the counted value matches the number of clocks indicated by the clock number signal NCLK, it causes a corresponding one of backlight control signals BLCON1 to BLCON4 to rise or fall in order to turn on or off a corresponding one of the backlights BL1 to BL4. A blank period BLANK is thus converted not to the number of horizontal lines but to the number of dot clocks in this embodiment. The on/off timings of the backlights BL1 to BL4 are set by the number of the dot clocks. This makes it possible to set the on-off timings of the backlights BL1 to BL4 with high precision.
The same effects as those of the above-described first embodiment are also obtainable in this embodiment. Further, in this embodiment, more precise setting of the turning-on timing and the turning-off timing is possible since these timings are set not by the number of horizontal lines but by the number of the clocks (the number of the dot clocks). As a result, the lighting periods of the backlights BL1 to BL4 can be made equal to one another with high precision.
The frequency of the internal clock signal ICLK is lower than the frequency of the clock signal CLK, so that the number of clocks indicated by an image clock signal PCLK outputted from an image detecting unit 36C and the number of clocks indicated by a blank-clock signal outputted from a blank-clock detecting unit 24 are smaller than those of the fourth embodiment. The frequency of the internal clock signal ICLK supplied to each of the circuits 36C, 24, 30C in the timing controller 10D is lower, so that the number of bits of a counter and so on counted by the clock signal can be reduced. As a result, circuit scale of these circuits can be reduced to reduce power consumption.
The internal clock signal ICLK is outputted from the oscillator 38D formed in the liquid crystal display device. Therefore, the frequency of the internal clock signal ICLK is independent from the frequency of the clock signal CLK supplied from an external part of the liquid crystal display device and thus is constant. The number of clocks of a lighting period ON that is set in advance in the ON/OFF timing calculating unit 28D is the number of clocks of the internal clock signal ICLK. As a result, the lighting periods ON of backlights BL1 to BL4 do not depend on the change in the frequency of the clock signal CLK and are thus always constant. The ON/OFF timing calculating unit 28D is designed to generate a clock number signal NCLK according to the frequency of the internal clock signal ICLK. The ON/OFF timing calculating unit 28D has the same basic function as that of the ON/OFF timing calculating unit 28C of the fourth embodiment.
The same effects as those of the first and fourth embodiments described above are also obtainable in this embodiment. Further, the turning-on timings and the turning-off timings of the backlights BL1 to BL4 are set by the number of the clocks of the internal clock signal ICLK in this embodiment, so that circuit scale of the timing controller 10D can be reduced to reduce power consumption. Further, the lighting periods ON of the backlights BL1 to BL4 can be kept constant, not depending on the frequency of the clock signal CLK. As a result, brightness of the backlights BL1 to BL4 can be made constant not only when a blank period BLANK changes but also when a frame period changes. Further, the frequency of the internal clock signal ICLK is set lower than the frequency of the clock signal CLK, so that circuit scale of the timing controller 10D can be made relatively small to enable relative reduction in power consumption.
The timing controller is configured such that a frequency divider 40E is added to the timing controller (
The same effects as those of the first and fifth embodiments described above are also obtainable in this embodiment. Further, in this embodiment, circuit scale of the timing controller can be made relatively small to enable relative reduction in power consumption, compared with a case where a clock signal CLK is used. Moreover, an expensive oscillator constituted of a crystal oscillator and so on is not required, which allows curtailed production cost of a liquid crystal display device.
The timing controller has an ON/OFF timing calculating unit 28F and a BLCON generating unit 30F in place of the ON/OFF timing calculating unit 28 and the BLCON generating unit 30 of the timing controller 10 (
The frame-head detecting unit 42F detects the pulse of an enable signal ENAB first generated after a blank period BLANK, and outputs a detecting signal DET (pulse) in synchronization with this detection. The ENABI generating unit 32A outputs an internal enable signal ENABI synchronizing with the enable signal ENAB, also in the blank period BLANK, as in the second embodiment.
The ON/OFF timing calculating unit 28F sets the turning-off timing of each of backlights BL1 to BL4 so that brightness of each of the backlights BL1 to BL4 lowers to the turn-off level before data of a subsequent frame image is supplied to a pixel electrode PE. Specifically, the turning-off timing of each of the backlights BL1 to BL4 is set earlier by a transition period TP2 than the supply timing of the data of the subsequent frame image to the pixel electrode PE in each of four areas corresponding to the backlights BL1 to BL4 in a liquid crystal panel 16.
When receiving the detecting signal DET while the backlight BL1 is on, the BLCON generating unit 30F forcibly deactivates a backlight control signal BLCON1. This means that the backlight BL1 is turned off in synchronization with the detecting signal DET even when the BLCON generating unit 30F cannot find the horizontal line number at which the backlight BL1 is turned off.
The same effects as those in the above-described first embodiment are also obtainable in this embodiment. Further, in this embodiment, the display of an image of the subsequent frame during the display of an image of the preceding frame can be prevented. As a result, blur of a moving image and so on can be prevented. Moreover, the backlight BL1 can be turned off without fail by the detecting signal DET even when the blank period BLANK gets shorter in accordance with the reduction in one frame period. As a result, it can be prevented that only the backlight BL1 keeps illuminating during one frame period. In other words, difference in brightness of the backlights can be prevented.
The timing controller has an ON/OFF timing calculating unit 28G in place of the ON/OFF timing calculating unit 28F of the timing controller (
The ON/OFF timing calculating unit 28G is formed to have, in addition to the function of the ON/OFF timing calculating unit 28F of the seventh embodiment, the function of the ON/OFF timing calculating unit 28A of the second embodiment. Therefore, the ON/OFF timing calculating unit 28G sets the turning-off timing of each of backlights BL1 to BL4 earlier than the supply timing of an image signal of the subsequent frame to a pixel electrode PE, and equally allots a blank period BLANK to lighting periods ON of the backlights BL1 to BL4. Incidentally, similarly to the third embodiment, the blank dividing unit 34A may execute rounding-off when the number of horizontal lines indicated by a blank-line signal BLN is not dividable by 4.
The same effects as those of the first, second, and seventh embodiments described above are also obtainable.
When judging that a data signal DATA0 (image signal) supplied from an external part of the liquid crystal display device via an external terminal is a still image, or when judging that images of a plurality of frames displayed in a predetermined pixel area of one screen are in one color or in similar colors, the image analyzing unit 44H activates a flicker preventing signal FLC. The backlight driving circuit 20H stops on/off control (turn on/off mode) of backlights BL1 to BL4 during a period in which the flicker preventing signal FLC is activated, and keeps the backlights BL1 to BL4 illuminating with predetermined brightness (a turning on mode). In other words, when images of the plural frames are in small motion, the turn on/off mode is changed to the turning-on mode. For example, brightness of the backlights BL1 to BL4 during the turning on mode is set to 80% of the maximum brightness. Since the on/off driving of the backlights BL1 to BL4 is not executed during the turning on mode, the occurrence of flicker due to on/off of the backlights BL1 to BL4 is prevented.
The same effects as those of the above-described first embodiment are also obtainable in this embodiment. Further, in this embodiment, the turning on mode is provided, which can prevent flicker from occurring when an image with small motion is displayed.
The same effects as those in the first and ninth embodiments described above are also obtainable in this embodiment.
Incidentally, in the examples explained in the above-described embodiments, the present invention is applied to the liquid crystal display device receiving the enable signal ENAB from the control device such as a personal computer. The present invention is not to be limited to such embodiments. For example, the present invention may be applied to a liquid crystal display device receiving a horizontal synchronous signal HSYNC and a vertical synchronous signal VSYNC from a control device. In this case, the present invention is realizable by the use of the horizontal synchronous signal HSYNC in place of the enable signal ENAB.
In the examples described in the first to sixth, ninth, and tenth embodiments described above, the fluorescent tubes are on with the maximum brightness while the backlights BL1 to BL4 are on and with 5% brightness of the maximum brightness when the backlights BL1 to BL4 are off. The present invention is not to be limited to such embodiments. For example, the fluorescent tubes may be turned off while the backlights BL1 to BL4 are off. Alternatively, the fluorescent tubes may be turned on with 90% brightness of the maximum brightness while the backlights BL1 to BL4 are on, so that the life span of the fluorescent tubes can be made longer. Brightness of the fluorescent tubes can be easily adjusted by the backlight driving circuit 20.
In the example described in the above-described third embodiment, the blank dividing unit 34B executes rounding-off when the number of the horizontal lines indicated by the blank-line signal BLN is not dividable by 4. The present invention is not to be limited to such an embodiment. For example, the blank dividing unit 34B may execute rounding-up.
The frame-head detecting unit 42F and the BLCON generating unit 30F of the above-described seventh embodiment may be provided in the liquid crystal display devices of the fourth to sixth embodiments.
The turning on mode of the above-described ninth and tenth embodiments may be provided in the liquid crystal display devices of the second to eighth embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-359733 | Oct 2003 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6815904 | Choi | Nov 2004 | B2 |
| 6906691 | Park et al. | Jun 2005 | B2 |
| 6963179 | Yu et al. | Nov 2005 | B2 |
| Number | Date | Country |
|---|---|---|
| 2002-006815 | Jan 2002 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20050083280 A1 | Apr 2005 | US |
