Patent Application
20060068576
The invention relates generally to the field of electronic interconnect systems, and more particularly to transfer lithography for high density interconnect circuits.
Integrated circuit functionality and complexity increase in tandem with ever shrinking device and electronic package geometries and footprints. Today, integrated circuit devices can be fabricated with features as small as 0.1 microns, with input/output pads as small as 0.2 micron pitch, or less. Input/output pad geometry and configuration for these devices are typically according to minimum interconnect features. That is to say that the input/output pad features and configuration are conventionally determined by an interconnect pitch and/or configuration capability, rather than a device or wafer capability.
Higher density multi-layer flexible circuits with finer signal trace pitches (e.g., less than 0.100 mm) have been fabricated for use in interconnect devices. Currently, the practical limit of interconnect pitch for multi-layer, flexible circuits available from commercial suppliers is approximately 0.100 mm with some capability in finer pitches (e.g., less than 100 mm) in prototype to low manufacturing volumes. Although alternative high density, fine pitch interconnect systems are contemplated, (e.g., carbon nanotubes), there currently exists an impediment or density barrier to interconnecting high density input/output devices to “systems.” This impediment results from functional performance, capability, and cost limitations of existing interconnect systems. In general, flexible printed circuits, i.e., flex interconnects, are constructed using thinner dielectrics and metals with finer geometries, and hence, flex interconnects typically allow for the circuit patterning at higher density as compared to their rigid counterparts. In the laboratory, multi-layer flexi interconnects with trace pitches as low as 0.030 mm pitch can be fabricated. However, even the most advanced flex interconnect technologies may be limited in achieving trace pitches under 0.030 mm due to the structural changes of the flex material during downstream processing and fabrication.
During a flexible printed circuit interconnect fabrication process implementing a flex (e.g., polyimide) substrate, the polymer base films are subjected to temperatures and mechanical forces that cause the polyimide to stretch, shrink and otherwise change in physical dimensions both during and upon completion of processing. These dimensional changes and instability can be minimized, but not to the extent that it is currently feasible to easily produce ultra fine pitch multi-layer flexible interconnect with trace pitches at or under 0.030 mm, at high yield.
Accordingly, there is a need to provide ultra fine pitch multi-layer flexible interconnect and circuits having electrical, mechanical and thermal stability.
In one aspect of the present technique a method for fabricating an interconnect is provided. The method comprises providing a carrier substrate, wherein the carrier substrate comprises a plurality of interconnect traces and a plurality of input/output contacts; providing a flexible substrate having a first side and a second side; disposing the second side of a sacrificial layer onto the first side of the flexible substrate to form a first assembly; disposing the carrier substrate onto the first assembly; and removing the carrier substrate and sacrificial layer to form the interconnect having the plurality of interconnect traces and the plurality of input/output contacts thereon.
In another aspect, an interconnect comprises a flexible substrate having a first side and a second side; and a plurality of interconnect traces having a pitch and a plurality of input/output contacts disposed on the second side of the flexible substrate, wherein the pitch comprises an interconnect trace and an interconnect space, and wherein the pitch is in a range from about 1 micron to about 20 microns.
In yet another aspect, a structure is provided which includes a carrier substrate; wherein the carrier substrate comprises a plurality of interconnect traces having a pitch and a plurality of input/output contacts, wherein the pitch comprises an interconnect trace and an interconnect space, and wherein the pitch is in a range from about 1 micron to about 20 microns; a flexible substrate having a first side and a second side; wherein the second side of the flexible substrate is disposed onto the carrier substrate; and a sacrificial layer having a first side and a second side, wherein the second side of the sacrificial layer is disposed on the first side of the flexible substrate.
In still another aspect, a detector for use in an imaging system is provided, which includes at least one sensor array configured for receiving waveform signals and converting the waveform signals to corresponding electrical signals; at least one electronic device configured for converting the electrical signals to corresponding digital signals; and an electronic circuit comprising an interconnect; wherein the interconnect comprises a flexible substrate having a first side and a second side; and a plurality of interconnect traces having a pitch and a plurality of input/output contacts disposed on the second side of the flexible substrate, wherein the pitch comprises an interconnect trace and an interconnect space, and wherein the pitch is in a range from about 1 micron to about 20 microns.
In yet another aspect, a method for fabricating an interconnect is provided. The method comprises providing a carrier substrate, wherein the carrier substrate comprises a plurality of interconnect traces and a plurality of input/output contacts; providing a flexible substrate having a first side and a second side, wherein the second side of the flexible substrate comprises a plurality of interconnect traces and a plurality of input/output contacts; providing a sacrificial layer having a first side and a second side; disposing the second side of the sacrificial layer onto the first side of the flexible substrate to form a first assembly; disposing the carrier substrate onto the first assembly; and removing the carrier substrate and the sacrificial layer to form the interconnect having the plurality of interconnect traces and the plurality of input/output contacts thereon.
In another aspect, a method for fabricating an interconnect is provided. The method comprises providing a first carrier substrate and a second carrier substrate, wherein the first and second carrier substrates comprise a plurality of interconnect traces and a plurality of input/output contacts; providing a flexible substrate having a first side and a second side; disposing the first carrier substrate onto the first side of the flexible substrate and disposing the second carrier substrate onto the second side of the flexible substrate; removing the first and second carrier substrates to form the interconnect having the plurality of interconnect traces and the plurality of input/output contacts thereon.
These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:
Various embodiments of an interconnect and a device assembly employing the same are depicted and described herein by way of example. However, those skilled in the art will recognize that the interconnect and interconnect package presented can be employed in a wide variety of implementations to connect, for example, an integrated circuit device to another component, such as another integrated circuit device, a flexible interconnect, or a printed circuit board subsystem, etc. The claims presented herein are intended to encompass all such implementations.
One aspect of the present technique described herein includes fabrication of an interconnect. Initially, a carrier substrate having a plurality of interconnect traces and a plurality of input/output (I/O) contacts is provided.
Generally, standard wafer processes, such as, photolithography and wet chemistry are employed to create interconnect traces and I/O contacts on the carrier substrate 10. As previously described, mechanical and chemical stability of the rigid carrier substrate material may enable fabrication of interconnect traces having finer pitch than if the interconnect traces were fabricated directly onto a flexible substrate. That is to say that current techniques may provide for the fabrication of ultra dense interconnect traces having trace pitches on the order of approximately 1 micron to 20 microns. In accordance with embodiments of the present techniques, such ultra density interconnects may be initially fabricated onto a carrier substrate 10, which may then be transferred to a flexible substrate, as described further below.
The flexible substrate 16 is disposed on the sacrificial layer 24 such that the first side 18 of the flexible substrate 16 faces the second side 28 of the sacrificial layer 24. The sacrificial layer 24 provides mechanical support during the fabrication of the interconnect. As the name suggests, the sacrificial layer 24 is separated from the flexible substrate 16 when employing the interconnect in a device. In one embodiment, the sacrificial layer 24 while acting as a mechanical support for the flexible substrate 16 may include a frame or a plane surface. The sacrificial layer 24 may further include, integrated circuit, semiconductor wafer, a printed circuit board, ceramic substrate, and/or low density interconnect circuits.
Further, the sacrificial layer 24 may be further supported by a mechanical support in the form of a stiffener. As will be appreciated, the stiffener may provide additional mechanical support during fabrication. The stiffener 32 may include materials, such as, but not limited to, organic, polymer, ceramic, metal, semiconductor, glass, or combinations thereof. In one embodiment, the first side 26 of the sacrificial layer is coupled to the stiffener 32. As will be appreciated, in an alternate embodiment, the stiffener may be omitted.
Further, the stiffener 32 and the sacrificial layer 24 may be etched using mechanical and/or chemical etching techniques, such as chemical mechanical polishing (CMP), plasma, KOH, reactive ion etching (RIE) or XeF2 etching, for example. The stiffener 32 and sacrificial layer 24 are etched until the materials are completely removed from the flexible substrate 16, as illustrated in
In step 44, the carrier substrate 10 is disposed on the flexible substrate 16 of the first assembly and attached using an adhesive, such as, polymeric adhesive. Typical adhesive systems that may be employed to attach the carrier substrate 10 to the flexible substrate 16 for use in this application may include thermosetting materials such as epoxies and acrylics and thermoplastics such as polyimides or liquid crystal polymers. As described herein, the adhesive may be removed or be an integral component of the high density flexible interconnect. Material compatibility of the substrate release process is one of the key adhesive requirements. For example, using KOH to remove silicon requires an adhesive system to have etch selectivity for the thin flexible circuit integrity. Other release processes rely on de-bonding the carrier substrate from the interconnect circuit and the adhesive system utilized is critical
In step 56, the sacrificial layer 24 and the carrier substrate 10 are thinned in order to form an interconnect as shown in
In another aspect of the present technique, one or more additional interconnect traces 12 and/or I/O contacts 14 on the second side 20 of the flexible substrate can be formed prior to attaching the carrier substrate 10 onto the second side 20 of the flexible substrate.
In one embodiment, the interconnect so formed is used in a detector for an imaging system. The detector includes one or more sensor arrays configured for receiving waveform signals, such as, and converting the waveform signals to corresponding electrical signals. In an exemplary embodiment, the waveform signals may be X-ray signals that may be employed in computed tomography detector. In another exemplary embodiment, the waveform signals may be acoustic signals that may be employed in ultrasound detector. The detector also includes one or more electronic devices configured for converting the electrical signals to corresponding digital signals and an electronic circuit employing an interconnect described above.
The X-ray source 50 is controlled by a power supply/control circuit 62 which furnishes both power and control signals for examination sequences. Moreover, detector 60 is coupled to detector acquisition circuitry 64, which commands acquisition of the signals generated in the detector 60. Detector acquisition circuitry 64 may also execute various signal processing and filtration functions, such as, for initial adjustment of dynamic ranges, interleaving of digital, and so forth.
In the depicted exemplary embodiment, one or both of the power supply/control circuit 62 and detector acquisition circuitry 64 are responsive to signals from a system controller 66. In some exemplary systems it may be desirable to move one or both of the detector 60 or the X-ray source 50. In such systems, a motor subsystem may also be present as a component of the system controller 66 to accomplish this motion. In the present example, the system controller 66 also includes signal processing circuitry, typically based upon a general purpose or application specific digital computer, associated memory circuitry for storing programs and routines executed by the computer, as well as configuration parameters and image data, interface circuits, and so forth.
Image processing circuitry 68 is also typically present in the X-ray imaging system. The image processing circuitry 68 receives acquired projection data from the detector acquisition circuitry 64 and processes the acquired data to generate one or more images based on X-ray attenuation.
One or more operator workstation 70 is also typically present in the X-ray imaging system. The operator workstation 70 allows an operator to initiate and configure an X-ray imaging examination and to view the images generated as part of the examination. For example, the system controller 66 is generally linked to operator workstation 70 so that an operator, via one or more input devices associated with the operator workstation 70, may provide instructions or commands to the system controller 66.
Similarly, the image processing circuitry 68 is linked to the operator workstation 70 such that the operator workstation 70 may receive and display the output of the image processing circuitry 68 on an output device 72, such as a display or printer. The output device 72 may include standard or special purpose computer monitors and associated processing circuitry. In general, displays, printers, operator workstations, and similar devices supplied within the system may be local to the data acquisition components or may be remote from these components, such as elsewhere within an institution or hospital or in an entirely different location. Output devices and operator workstations that are remote from the data acquisition components may be linked to the image acquisition system via one or more configurable networks, such as the internet, virtual private networks, and so forth. As will be appreciated by one of ordinary skill in the art, though the system controller 66, image processing circuitry 68, and operator workstation 70 are shown distinct from one another in
While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
