Claims
- 1. A circuit block for use in programmable logic devices, comprising:
- a decoder;
- a random access memory having a plurality of bits addressed by said decoder, wherein said random access memory provides a plurality of outputs, each corresponding to a column of memory, wherein each column of memory contains 16 bits of storage;
- a read buffer connected to said random access memory for reading data output therefrom, wherein said read buffer provides a separate read buffer for each memory column;
- a write driver connected to said random access memory for inputting data thereto;
- means for configuring the circuit block to function as user-writable memory or to provide a logic function; and
- a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
- 2. A circuit block for use in programmable logic devices, comprising:
- a decoder;
- a random access memory having a plurality of bits addressed by said decoder, wherein said random access memory provides a plurality of outputs, each corresponding to a column of memory, wherein said memory columns are capable of being configured to provide a single output;
- a read buffer connected to said random access memory for reading data output therefrom, wherein said read buffer provides a separate read buffer for each memory column;
- a write driver connected to said random access memory for inputting data thereto;
- means for configuring the circuit block to function as user-writable memory or to provide a logic function; and
- a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
- 3. A circuit block for use in programmable logic devices, comprising:
- a decoder;
- a random access memory having a plurality of bits addressed by said decoder, wherein said random access memory provides a plurality of outputs, each corresponding to a column of memory, wherein said memory has n columns each having m bits of storage, and wherein said memory columns are capable of being configured as an n output by m bit memory, or as a single output by (n.times.m) bit memory;
- a read buffer connected to said random access memory for reading data output therefrom, wherein said read buffer provides a separate read buffer for each memory column;
- a write driver connected to said random access memory for inputting data thereto;
- means for configuring the circuit block to function as user-writable memory or to provide a logic function; and
- a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
- 4. The circuit block of claim 3, wherein m=16.
- 5. The circuit block of claim 4, wherein n=4.
- 6. The circuit block of claim 5, wherein said memory columns are further capable of being configured as a 2 output by 32 bit memory.
Parent Case Info
This is a Division, of application Ser. No. 07/575,449, filed Aug. 30, 1990 pending, which is a division of Ser. No. 414,695, filed Sep. 29, 1989, now U.S. Pat. No. 4,975,601 .
US Referenced Citations (5)
Divisions (2)
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Number |
Date |
Country |
Parent |
575449 |
Aug 1990 |
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Parent |
414695 |
Sep 1989 |
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