S. Bhattacharya et al., H-scan: A high level alternative to full scan testing with reduced area and test application overhead, VLSI test Symposium, Apr. 1996, pp. 74-80. |
M. Potkonjak et al., "Behavioral synthesis of area-efficient testable design using interaction between hardware sharing and partial scan", IEEE Trans. on computer-aided design; pp.1141-1154, Sept. 1995. |
S. Narayanan et al., "Reconfigurable scan chains: A novel approach to reduce test application time", Proceedings of ICCAD, pp. 710-715, Sep. 1993. |
C. C. Lin et al., "Cost-free Scan: A low overhead scan path design methodology", Proceedings of ICCAD, pp. 528-533, Jul. 1995. |
T. Riesgo et al., "CAD in test", Industrial electronics, 1995 International Symposium, pp. 33-38, Jan. 1995. |
L. Avra, "Allocation and assignment in high-level synthesis for self-testable data paths", International test conference, 1991, pp. 463-472, Jan. 1991. |
Thomas W. Williams et al., "Design for Testability-A Survey", Proceedings of the IEEE, vol. 71, No. 1, Jan. 1983, pp.311-325. |
E.B. Eichelberger et al., "A Logic Design Structure for LSI Testability", 14.sup.th Design Automation Conference, ACM/IEEE, Jun. 1977, pp. 462-468. |
Kwang-Ting Cheng et al., "A Partial Scan Method for Sequential Circuits with Feedback", IEEE Transactions on Computers, vol. 39, No. 4, Apr. 1990, pp. 544-548. |
D.H. Lee et al., "On Determining Scan Flip-Flops in Partial-Scan Designs", Proceedings of the International Conference on Computer-Aided Design, Nov. 1990, pp. 322-325. |
Vivek Chickermane et al., "An Optimization Based Approach to the Partial Scan Design Problem", 1990 International Test Conference, Sep. 1990, pp 377-386. |
Bapiraju Vinnakota et al., "Synthesis of Sequential Circuits for Parallel Scan", Proc. of the European Conference on Design Augomation, Mar. 1992, pp. 366-370. |
Sridhar Narayanan et al., "Reconfigurable Scan Chains: A Novel Approach to Reduce Test Application Time", Proc. of ICCAD, 1993, pp. 710-715. |
Catherine H. Begotys et al., "Integraion of Algorithmic VLSI Synthesis with Testabilty Incorporation", IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 409-416. |
Chung-Hsing Chen et al., "Structural and Behavioral Synthesis for Testability Techniques", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 6,Jun. 1994, pp. 777-785. |
Subhrajit Bhattacharya et al., "Clock Period Optimization During Resource Sharing and Assignment", 31.sup.st ACM/IEEE Design Automation Conference, 1994, pp. 195-200. |
Thomas Niermann et al., "HITEC: A Test Generation Package for Sequential Circuits", Proc. EDAC, 1991, pp. 214-218. |
S.T. Chakradhar et al., "A Transitive Closure Algorithm for Test Generation", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 12, No. 7, Jul. 1993, pp. 1015-1028. |