Low-density parity check decoding

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention will now be described, by way of example only, with reference to the enclosed views, wherein:

FIG. 1 is a functional block diagram of a digital communication system.

FIG. 2 is a graphical representation of an LDPC code.

FIG. 3 is a graphical representation of the non-null elements of a parity check matrix.

FIG. 4 is a graphical representative of the parity section of an exemplary code structure adapted for use in an embodiment.

FIG. 5 is a functional block diagram representative of a top-level architecture of a decoder according to an embodiment.

DETAILED DESCRIPTION OF THE INVENTION

By way of introduction of a detailed description of preferred embodiments of the arrangement described herein invention, some of the theoretical principles underlying such an arrangement will now be briefly discussed by way of direct comparison with the related art described in the foregoing.

As a first point, the MIN-SUM (MS) approximation will be shown to be a straightforward simplification of the check-node computation.

In fact:

$\begin{matrix} Φ^{- 1} (\sum_{i} Φ (x_{i})) ≅ \min_{i} x_{i} & Eq 14 \end{matrix}$

The reliability of the messages coming out of a check-node update can be expected to be dominated by the least reliable incoming message. The MS outputs are, in modulus, slightly larger than those output by a non-approximated check-node processor. This results in a significant error rate degradation.

For this reason, Chen et al. (already cited in the foregoing) have proposed to resort to Normalized-MS (N-MS) to partially compensate for these losses: N-MS typically consists of a simple multiplication of the output messages by a scaling factor. The factor can be optimized through simulations or, in a more sophisticated way, with density evolution as disclosed by Chen et al.

This approach recovers most of the performance gap caused by MS and makes MS a valid alternative to a full processing approach. An almost equivalent alternative to the N-MS is the Offset-MIN-SUM (O-MS), again disclosed by Chen et al., that performs slightly worse than N-MS.

A MS decoder does not require knowledge of the noise variance, which is of great interest when the noise variance in unknown or hard to be determined. More sophisticated approximations are able to perform nearly the same as a full precision approach, but generally require a data dependent correction term that makes the check-node processor more complex. This specific issue has been investigated in the art (see, e.g., Zarkeshvari, F. Banihashemi, A. H.: On implementation of min-sum algorithm for decoding low-density parity-check (LDPC) codes: GLOBECOM '02. IEEE Vol. 2, 17-21 November 2002, pp. 1349-1353).

Parallel or partially parallel architectures employ a multiplicity of check-node processors. For this reason any simplification of this computation kernel is of particular interest. When MS is adopted, the same modulus is shared by all outgoing messages from a check-node update processor; its value is equal to the smaller modulus among the incoming messages. The only exception is the outgoing message that corresponds to bit whose incoming massage has the smaller modulus. The modulus of such outgoing message is equal to the second smaller among the incoming messages.

Hence, the minimum check-to-bit information to be stored is much less in comparison with the approaches described so far. For that reason, Normalized MS approximation, with a memory efficient approach, is proposed here in conjunction with the layered decoding (L-SPA) to compensate for the MS performance degradation thanks to the faster convergence given by the scheduling modification. While a more detailed analysis of the storage capability will be provided in the following, with a detailed comparison with the other cases, it will noted that, by adopting the approach described herein, storing (i) two moduli; (ii) the signs of all the outgoing messages; (iii) the position of the least reliable message will suffice. The new approach is capable of outperforming conventional SPA with the same number of iterations, while requiring about 70% less memory. The approach considered here (which may be designated Layered-Normalized-MIN-SUM, i.e., L-N-MS) applies a memory efficient normalized MIN-SUM approach to a layered decoding schedule is schematically represented below.

Λ_j= λ_j∀ j

for k = 1:N_ite

for i = 1:nc

for j ∈ V(i)

if j ≠ M(i)

{\tilde{Q}}_{ji} = Λ_{j} - R_{i}^{1} S_{ij}

else

{\tilde{Q}}_{ji} = Λ_{j} - R_{i}^{2} S_{ij}

R_{i}^{1} = \min \langle {\tilde{Q}}_{ji} \rangle / α

M (i) = \underset{j}{\arg} \min \langle {\tilde{Q}}_{ji} \rangle

R_{i}^{2} = \min_{j \neq M (i)} \langle {\tilde{Q}}_{ji} \rangle / α

for j ∈V(i)

S_{ij} = (sign ({\tilde{Q}}_{ji}) • \prod_{m \in V (i)} sign ({\tilde{Q}}_{mi}))

if j ≠ M(i)

Λ_{j} = {\tilde{Q}}_{ji} + R_{i}^{1} S_{ij}

else

Λ_{j} = {\tilde{Q}}_{ji} + R_{i}^{2} S_{ij}

where R_i¹and R_i², are the smallest and second smallest check-to-bit message modulus, M(i) is the least reliable bit in equation i, S_miare the signs of the outgoing messages and α is the scaling factor of N-MS.

Performance of the L-M-MS proposed herein can be compared with performance achievable with: a layered decoding and pure MS (i.e., without normalization factor) (L-MS); with layered decoding algorithm (L-SPA); and with a conventional SPA.

For instance a meaningful comparison can be performed at 25 iterations. As a first example, a structured LDPCC code, designed by the team of Prof. Wesel (University of California Los Angeles) has been used for the comparison. Code is designed with same graph conditioning adopted in Vila Casado A. I.; Weng W.; Wesel R. D.: “Multiple Rate Low-Density Parity-Check Codes with Constant Block Length”, Asilomar Conf. on Signals, Systems and Computers, Pacific Grove, Calif., 2004. The code is 1944 bits long with rate ⅔. It is designed with a combination of 8×24=192 cyclically shifted identity matrices and null matrices of size 81×81. The number of edges is equal to 7613 with maximum variable degree equal to 8 and maximum check degree equal to 13. The parity part is organized as described in FIG. 4.

The upper right matrix D is defined (parity section only) by Eq 15 below for a rate ⅔ code structure.

$\begin{matrix} D = [\begin{matrix} 0 & 0 & \dots & 0 & 0 & 0 & 0 \\ 1 & 0 & \dots & 0 & 0 & 0 & 0 \\ 0 & 1 & \dots & 0 & 0 & 0 & 0 \\ 0 & 0 & \dots & 0 & 0 & 0 & 0 \\ ⋮ & ⋮ & ⋮ & ⋮ & ⋮ & ⋮ & ⋮ \\ 0 & 0 & \dots & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 \end{matrix}] & Eq 15 \end{matrix}$

The results show L-N-MS performs slightly better than conventional SPA, but requires much simpler check-node processing and a dramatically smaller amount of memory. The gap between L-SPA and L-MS is mostly recovered by means of the normalization factor. The normalization factor α has been optimized through simulations focusing on Frame Error Rate—FER equal to 10⁻²with the resulting value equal to 1.35.

As a second example, a high rate structured LDPCC code of similar size has been selected among those proposed in Eleftheriou E.; Ölcer S.: Low density parity-check codes for digital subscriber lines, in Proc., ICC'2002, New York, N.Y., pp. 1752-1757. The code has a linear encoding complexity and supports layered decoding. It is 2209 bits long and it has rate 0.9149. In this case L-N-MS performs even slightly better than the L-SPA. An explanation could be found in the code structure that may have more short cycles compared to the previous example, so that SPA becomes less efficient. The normalization factor α was equal to 1.3.

Fixed-point implementation of N-MS would require a multiplication by a factor with a high accuracy in the quantization level and a significant complexity due to the operator itself. However, it is possible to simplify the normalization procedure at the cost of negligible performance loss.

The normalization can be implemented very efficiently with the following approach:

Q/α1α≅Q−(Q>>s) Eq 16

where the operator (x>>y) represent a y bits right shift of message x. For both examples s has been chosen equal to 2, that corresponds to a=1.333.

One may define a uniform quantization scheme (N_b,p), where N_bis the number of bits (including sign) and p is the fraction of bits dedicated to the decimal part (i.e., the quantization interval is 2^−p). The adopted quantization schemes are the best for a given number of bits N_b. For the rate ⅔ code not even 8 bits are sufficient to perform close to the floating point precision. However, if the same quantization scheme is applied to decode a similar rate ⅔ code with size 648 bits, it results that L-N-MS with (8-4) performs better than floating point SPA at 12 iterations.

This result is consistent with the results reported in Zarkeshvari et al. (already cited), where it has been noted that the MS approximation works pretty well with short codes and quantized messages. For the higher rate code even 6 bits were found to lead to negligible losses.

The N-MS approach allows a significant reduction of the memory to store the check-to-bit messages R_ij. In fact, the amount of memory turns out to be: (i) 2*nc*(N_b−1) bits for the modulus of the two least reliable check-to-bit messages of each check (where nc is the number of checks); (ii) the sign of all check-to-bit messages that result in E bits; (iii) the position of the least reliable message in the check that results in nc*ceil(log2(dc)) bits, where dc is (maximum) check-node degree, and [ceil] denotes the ceiling operator.

Table 2 below summarizes the results of comparison of the memory requirements for the approaches presented so far. Specifically, Table 2 refers to the memory needed to store the messages R_ijand Q_ijand reports the results of comparison between conventional check-node and memory efficient MS approximation applied to different decoding algorithms.

Algo.
Memory [bits]

SPA
2 * E * N_b

MS
E * N_b+ 2 * nc * (N_b− 1) + E + ceil (log2(dc))

M-SPA
(E + 2 * n) * N_b

M-MS
2 * n * N_b+ 2 * nc * (N_b− 1) + E + ceil (log2(dc))

L-SPA
(E + n) * N_b

L-MS
n * N_b+ 2 * nc * (N_b− 1) + E + ceil (log2(dc))

The results in terms of memory requirements for the simulated codes indicate that the L-N-MS approach proposed herein requires 70% and 76% less memory than the conventional implementations of the SPA algorithm for rate ⅔ code and rate 0.9149 code, respectively. At the cost of some minor performance losses, memory requirements can be reduced by a factor 24%, 42% and 50% when the memory efficient MS solution is applied to SPA, M-SPA, and L-SPA, respectively, for the rate ⅔ code considered. For the rate 0.9149 code, the reduction amounts to 24%, 51% and 61%.

A “memory efficient” MS entails some significant, potential advantages that relate to the implementation of high-speed parallel decoders.

A first advantage lies in that a check-node requires much less input/output bits, so that routing problems can be scaled-down compared to a conventional approach. Secondly, in vectorized decoders explicitly dedicated to structured LDPCC (see, Novichkov et al. and WO-A-02/103631—both already cited), memory paging is designed so that all messages belonging to the same non-null sub-block in the parity check matrix are stored in the same memory word. A switch-bar is then adopted to cyclically rotate the message after/before the R/W operation. The approach discussed herein provides for the possibility of implementing switch-bars for A only.

FIG. 5 is a functional block diagram of an embodiment of a decoder.

With reference to the general layout of FIG. 1, the decoder 20 is intended to be located downstream of the demodulator 18 to produce decoded data 22. The decoder 20 receives as its input the LLR values produced by the demodulator 18 (the demodulator may be implemented in a way to provide these values directly). The decoder 20 processes these LLR to retrieve the decoded data 22.

Referring to FIG. 5, the decoder 20 is configured to receive from the demodulator 18 initial values) λ_jfor initialization (i.e., Λ_j=λ_jfor each j) and to produce as an output from a memory block designated A the messages Λ_jwhich are representative of the a-posteriori probability of the output decoded data. Specifically, the decoder receives as its input the logarithm of the ratio of the likelihood for each bit, i.e., λ_j; the decoder yields Λ_j, i.e., the logarithm of the ratio of the a-posteriori probabilities.

The decoder 20 herein is assumed (just by way of example, with no intended limitation of the scope of the invention) to operate with “parallelism 3”, i.e., a structured LDPCC with subblock size equal to 3 is assumed. The basic layout of the arrangement implemented in the decoder of FIG. 5 is repeated below for immediate reference.

Λ_j= λ_j ∀ j

for k = 1:N_ite

for i = 1:nc

for j ∈ V(i)

if j ≠ M(i)

{\tilde{Q}}_{ji} = Λ_{j} - R_{i}^{1} S_{ji}

else

{\tilde{Q}}_{ji} = Λ_{j} - R_{i}^{2} S_{ij}

R_{i}^{1} = \min \langle {\tilde{Q}}_{ji} \rangle / α

M (i) = \underset{j}{\arg} \min \langle {\tilde{Q}}_{ji} \rangle

R_{i}^{2} = \min_{j \neq M (i)} \langle {\tilde{Q}}_{ji} \rangle / α

for j ∈ V(i)

S_{ij} = (sign ({\tilde{Q}}_{ji}) \cdot \prod_{m \in V (i)} sign ({\tilde{Q}}_{mi}))

if j ≠ M(i)

Λ_{j} = {\tilde{Q}}_{ji} + R_{i}^{1} S_{ij}

else

Λ_{j} = {\tilde{Q}}_{ji} + R_{i}^{2} S_{ij}

where R_i¹and R_i²are the smallest and second smallest check-to-bit message modulus, M(i) is the least reliable bit in equation i, S_miare the signs of the outgoing messages and α is the scaling factor of N-MS.

The memory block designated A stores the messages Λ_j; each word contains the values belonging to three consecutive bit nodes.

The memory block designated S stores the signs S_ij; three signs belonging to three consecutive messages └S_3i,3jS_3i+1,3j+1S_3i+2,3j+2┘ are arranged together to form a memory word.

The memory block designated R contains three messages related to the minimum and second minimum and minimum position, i.e., the memory block designated R contains three messages related to i) the value of the minimum, ii) the value of the second minimum and iii) the minimum position.

The messages are arranged together in such a way that all the messages related to the check equations that must be run in parallel (a super-code) can be read simultaneously; an example of memory word content is given below:

$\begin{matrix} [\begin{matrix} [\begin{matrix} R_{3 i}^{1} & R_{3 i}^{2} & M_{3 i} \end{matrix}] \\ [\begin{matrix} R_{3 i + 1}^{1} & R_{3 i + 1}^{2} & M_{3 i + 1} \end{matrix}] \\ [\begin{matrix} R_{3 i + 2}^{1} & R_{3 i + 2}^{2} & M_{3 i + 2} \end{matrix}] \end{matrix}] & Eq 17 \end{matrix}$

The input messages to the memory block A and the output messages therefrom are rotated back and forward according to the proper shift values.

In the embodiment shown herein, this function is performed via switch-bars 100, 102 arranged at the input and the output of the memory block A.

The messages coming out of the memory blocks A, S, and R are demultiplexed towards the proper blocks Q configured to perform the computation of the values {tilde over (Q)}_jiIn the embodiment shown herein, the demultiplexing is performed via three demultiplexers 104, 106, and 108 each serving a respective one of three blocks Q. As illustrated, a bit-to-check module 120 comprises a plurality of bit-to-check generators Q.

The three blocks Q in turn feed a corresponding block CNP (Check Node Processor). The CNP blocks are configured to perform the following functions:

- i) the search of the minimum, its position and the second minimum (R_i¹; R_i². M_i);
- ii) the computation of output signs S_ij; and
- iii) the computation of the new a-posteriori probabilities Λ_j.

The output messages from the CNP blocks are then multiplexed via multiplexer blocks 110, 112, and 114 to be written back at the proper addresses in the memory blocks A, S, and R. As illustrated, a check node module 130 comprises a plurality of check node processors CNP.

The present invention is not limited to the embodiments described above. For instance, the foregoing detailed description has set forth various embodiments of the devices and/or processes via the use of block diagrams, schematics, and examples. Insofar as such block diagrams, schematics, and examples contain one or more functions and/or operations, it will be understood by those skilled in the art that each function and/or operation within such block diagrams, flowcharts, or examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof. In one embodiment, the present subject matter may be implemented via ASICs. However, those skilled in the art will recognize that the embodiments disclosed herein, in whole or in part, can be equivalently implemented in standard integrated circuits, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more controllers (e.g., microcontrollers) as one or more programs running on one or more processors (e.g., microprocessors), as firmware, or as virtually any combination thereof, and that designing the circuitry and/or writing the code for the software and or firmware would be well within the skill of one of ordinary skill in the art in light of this disclosure.

All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Claims

1. A method of decoding Low Density Parity Check (LDPC) encoded signals propagated over a channel by iteratively producing messages representative of an a-posteriori probability of output decoded signals as a function of check-to-bit messages produced from bit-to-check messages via check-node update computation, wherein said check-node update computation is performed as a MIN-SUM approximation and a reliability of output messages from the check-node update computation is determined by one of a least or second least reliable incoming message, the method comprising: generating bit-to-check messages for parity check from a last version of the messages representative of the a-posteriori probability and past check-to-bit messages;identifying a smallest modulus and a second smallest modulus of the bit-to-check messages, signs of the output messages and a position of the least reliable incoming message; andproducing an updated version of the messages representative of the a-posteriori probability of output decoded signals as a function of the smallest or the second smallest of the past check-to-bit messages, the signs of the output messages and the position of the least reliable incoming message.
2. The method of claim 1, including the step of multiplying the output messages from said check-node update by a scaling factor to compensate for effects of the MIN-SUM approximation applied in the computation of said reliability.
3. The method of claim 1, including the step of running in parallel a plurality of check-node update computations and the step of arranging in parallel to be read simultaneously all the messages related to said plurality of check-node update computations run in parallel.
4. The method of claim 1, including the step of implementing said check-node update computations as a search of: a first and a second minimum for said smallest and the second smallest of said bit-to-check messages, respectively; andthe position of said first minimum as the position of said least reliable incoming message.
5. A decoder for decoding Low Density Parity Check (LDPC) encoded signals propagated over a channel, wherein said decoding produces messages representative of an a-posteriori probability of output decoded signals as a function of check-to-bit messages produced from bit-to-check messages via check-node update computation, the decoder including: circuitry configured to perform said check-node update computation as a MIN-SUM approximation wherein a reliability of output messages from said check-node update computation is determined by one of a least or second least reliable of the incoming bit-to-check messages;check node processor circuitry configured to identify a smallest and a second smallest modulus of said check-to-bit messages, the signs of said output messages and the position of said least reliable incoming message M(i), and producing said messages representative of the a-posteriori probability of output decoded signals as a function of said smallest and the second smallest modulus of said check-to-bit messages, signs of said output messages and the position of said least reliable incoming message.
6. The decoder of claim 5, further comprising: circuitry configured to multiple the output messages from said check-node update by a scaling factor α compensate for effects of MIN-SUM approximation applied in the computation of said reliability.
7. The decoder of claim 5, further comprising: circuitry configured to run in parallel a plurality of check-node update computations and arranged in parallel to read simultaneously all messages related to said plurality of check-node update computations run in parallel.
8. The decoder of claim 5 wherein said check node circuitry includes at least one check-node processor for performing said update computations as a search of: a first and a second minimum for said smallest and the second smallest of said bit-to-check messages, respectively; andthe position M(i) of said first minimum as the position of said least reliable incoming message.
9. A decoder for decoding Low Density Parity Check (LDPC) encoded signals propagated over a channel, wherein said decoding produces messages representative of an a-posteriori probability of output decoded signals as a function of check-to-bit messages produced from bit-to-check messages via check-node update computation, the decoder including: circuitry configured to perform said check-node update computation as a MIN-SUM approximation wherein a reliability of the output messages from said check-node update computation is determined by a least and second least reliable incoming message;memory circuitry configured for storing a smallest and a second smallest modulus of said check-to-bit messages, signs of said output messages and a position of said least reliable incoming message, to produce therefrom an updated version of said messages representative of the a-posteriori probability of output decoded signals.
10. The decoder of claim 9 wherein the memory includes at least one modulus memory block for storing said smallest and second smallest modulus of said check-to-bit messages as well as said position of said least reliable incoming message.
11. The decoder of claim 9 wherein the memory includes an a-posteriori probability memory block for storing said messages representative of the a-posteriori probability, said a-posteriori probability memory block arranged in word locations, each word location adapted for containing values of a plurality of bit nodes.
12. The decoder of claim 11, including at least one shifter element to rotate by shift values the input messages to said a-posteriori probability memory block and the output messages therefrom.
13. The decoder of claim 11, wherein said at least one shifter element includes a switch-bar.
14. The decoder of claim 9 wherein the memory includes a sign memory block for storing said signs of said check-to-bit messages, said sign memory block arranged in word locations, each word location adapted for containing a plurality of signs belonging to plural messages arranged together to form a memory word.
15. The decoder of claim 9 wherein: the memory includes an a-posteriori probability memory block for storing said messages representative of a-posteriori probability; anda sign memory block for storing said signs of said check-to-bit messages, wherein the circuitry configured to perform said check node update computation is configured to produce said messages representative of the a-posteriori probability of output decoded signals as a function of said smallest modulus and the second smallest modulus of said check-to-bit messages, the signs of said check-to-bit messages and the position of said least reliable incoming message; andthe decoder further comprises demultiplexer circuitry configured to demultiplex outputs from said memory circuitry as inputs to the circuitry configured to perform the check node update computation.
16. The decoder of claim 15, wherein said circuitry configured to perform the check node update computation includes at least one check-node processor fed for performing said update computations as a search of: a first and a second minimum for said smallest and the second smallest of said check-to-bit messages, respectively; anda position of said first minimum as the position of said least reliable incoming message.
17. The decoder of claim 16, further including multiplexer circuitry configured to multiplex outputs from the at least one check-node processor towards said memory circuitry.
18. A method of decoding Low Density Parity Check (LDPC) encoded signals propagated over a channel by producing messages representative of the a-posteriori probability of output decoded signals, the method including the joint adoption of minimum sum (MIN-SUM) approximation and layered decoding.
19. The method of claim 18 wherein the MIN-SUM approximation is normalized.
20. A computer program product for decoding Low Density Parity Check (LDPC) encoded signals propagated over a channel by producing messages representative of the a-posteriori probability of output decoded signals, the product loadable in the memory of at least one computer and including software code portions for performing the steps of: iteratively producing messages representative of an a-posteriori probability of output decoded signals as a function of check-to-bit messages produced from bit-to-check messages via check-node update computation, wherein said check-node update computation is performed as a minimum-sum approximation and a reliability of output messages from said check-node update computation is determined by one of a least or second least reliable incoming message;generating bit-to-check messages for parity check from a last version of the messages representative of the a-posteriori probability and past check-to-bit messages;identifying a smallest modulus and a second smallest modulus of said bit-to-check messages, signs of said output messages and a position of said least reliable incoming message; andproducing an updated version of said messages representative of the a-posteriori probability of output decoded signals as a function of one of said smallest or the second smallest of modulus, the signs of said output messages and the position of said least reliable incoming message.
21. The computer program product of claim 20 wherein the minimum-sum approximation is normalized.
22. A decoder for decoding low-density-parity-check encoded signals, the decoder comprising: a probability memory block for storing a set of check-to-bit messages;a bit-to-check module configured to generate a set of bit-to-check messages from the set of check-to-bit messages;a check node module configured to output a smallest and a second smallest modulus of messages in the set of bit-to-check messages, an identifier of a position associated with the smallest modulus, and a revised set of check-to-bit messages;a modulus memory block configured to store the smallest modulus, the identifier and the second smallest modulus; anda signs memory block configured to store signs of the revised set of check-to-bit messages.
23. The decoder of claim 22, further comprising: a plurality of demultiplexers coupled between the memory blocks and the bit-to-check module, wherein the bit-to-check module comprises a plurality of bit-to-check generators; anda plurality of multiplexers coupled between the check node module and the memory blocks, wherein the check node module comprises a plurality of check node processors.
24. The decoder of claim 23, further comprising: a first shifter coupled between a multiplexer in the plurality of multiplexers and an input to the probability memory block; anda second shifter coupled between an output of the probability memory block and a demultiplexer in the plurality of demultiplexers.
25. A method of decoding low density parity check signals, comprising: storing a set of check-to-bit messages, a smallest modulus, a position associated with the smallest modulus, a second smallest modulus, and a set of signs;generating a set of bit-to-check messages based on the set of check-to-bit messages, the smallest modulus, the position associated with the smallest modulus, the second smallest modulus, and the set of signs; andrevising the set of check-to-bit messages based on the set of bit-to-check messages, the smallest modulus, the position associated with the smallest modulus, the second smallest modulus and the set of signs.
26. The method of claim 25 wherein the generating the set of bit-to-check messages comprises: when the position associated with the smallest modulus corresponds to a position of a message in the set of check-to-bit messages, generating a message in the set of bit-to-check messages based on the second smallest modulus; andwhen the position associated with the smallest modulus does not correspond to the position of the message in the set of check-to-bit messages, generating the message in the set of bit-to-check messages based on the smallest modulus.
27. The method of claim 25 wherein the revising the set of check-to-bit messages comprises applying a scaling factor.
28. The method of claim 25, further comprising: revising the smallest modulus, the position associated with the smallest modulus, the second smallest modulus, and the set of signs.
29. A computer-readable memory medium containing instructions that cause a processor to perform a method of decoding low density parity check signals, the method comprising: storing a set of check-to-bit messages, a smallest modulus, a position associated with the smallest modulus, a second smallest modulus, and a set of signs;generating a set of bit-to-check messages based on the set of check-to-bit messages, the smallest modulus, the position associated with the smallest modulus, the second smallest modulus, and the set of signs; andrevising the set of check-to-bit messages based on the set of bit-to-check messages, the smallest modulus, the position associated with the smallest modulus, the second smallest modulus and the set of signs.
30. The computer-readable memory medium of claim 29 wherein the generating the set of bit-to-check messages comprises: when the position associated with the smallest modulus corresponds to a position of a message in the set of check-to-bit messages, generating a message in the set of bit-to-check messages based on the second smallest modulus; andwhen the position associated with the smallest modulus does not correspond to the position of the message in the set of check-to-bit messages, generating the message in the set of bit-to-check messages based on the smallest modulus.
31. The computer-readable memory medium of claim 29 wherein the revising the set of check-to-bit messages comprises applying a scaling factor.
32. The computer-readable memory medium of claim 29, wherein the method further comprises: revising the smallest modulus, the position associated with the smallest modulus, the second smallest modulus, and the set of signs.

Provisional Applications (1)

	Number	Date	Country
	60787063	Mar 2006	US

Low-density parity check decoding

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CPC

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Abstract

Description

Claims

Provisional Applications (1)