LOW LATENCY MEMORY ACCESS

Abstract

A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device’s primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.

Description

Claims

1. (canceled)

2. A memory component, comprising: a memory core;synchronous control circuitry to, based on the memory component being in a first mode, access the memory core in response to first command, first control, and first address information received via a first synchronous sampling of signals at a first set of links using a first timing signal; andasynchronous control circuitry to, based on the memory component being in a second mode, access the memory core in response to second command, second control, and second address information received via a first asynchronous sampling of signals at the first set of links and the first asynchronous sampling of signals at a second set of links using a second timing signal received via a second timing signal interface.

3. The memory component of claim 2, wherein the asynchronous control circuitry is to activate a row in a bank of the memory core in response to the second command, second control, and second address information.

4. The memory component of claim 2, wherein, in the first mode, information is to be communicated bidirectionally by the memory component, synchronously, via the second set of links, using the second timing signal.

5. The memory component of claim 2, wherein, in the second mode, information is to be communicated bidirectionally by the memory component, synchronously, via the second set of links, using the second timing signal.

6. The memory component of claim 2, wherein a first synchronous interface that samples the first set of links synchronously using the first timing signal when in the first mode and a second synchronous interface that communicates synchronously with the second set of links using the second timing signal when in the first mode are not to be sampling synchronously when in the second mode.

7. The memory component of claim 2, wherein, while in the second mode and while the first timing signal is in an inactive signal, at least one transition of a third timing signal initiates the first asynchronous sampling of the first set of links to receive the second command, the second control, and the second address information.

8. The memory component of claim 7, wherein a signal interface is to be used, in the first mode, to receive a power control signal and is to be used, in the second mode, to receive the third timing signal.

9. The memory component of claim 7, wherein an exit from the second mode to the first mode is to be initiated by activating the first timing signal.

10. The memory component of claim 7, wherein the at least one transition of the third timing signal initiates an exit from the second mode.

11. A memory component, comprising: synchronous control circuitry to at least, in a first mode of the memory component, send first control signals to a memory core that activate a first row in response to first command, address, and control signals synchronously received with respect to a first externally received timing reference; andasynchronous control circuitry to at least, in a second mode of the memory component, send second control signals to the memory core that activate a second row in response to second command, address, and control signals received in response to at least one transition of a second externally received timing reference.

12. The memory component of claim 11, wherein the second mode of the memory component is a lower power mode with respect to the first mode.

13. The memory component of claim 11, wherein, in the second mode of the memory component, the memory component is to also communicate data synchronously with respect to a third externally received timing reference.

14. The memory component of claim 13, wherein, in the second mode of the memory component, the memory component is to, via a first interface, receive a portion of the second command, address and control signals and the memory component is to, via a second interface, receive a remaining portion of the second command, address and control signals in response to at least one transition of the third externally received timing reference.

15. The memory component of claim 14, wherein the remaining portion of the second command, address and control signals comprises address signals.

16. The memory component of claim 11, wherein, in the first mode, when the first externally received timing reference is active, the first command, address, and control signals are enabled to be received by an enable signal on a signal input.

17. The memory component of claim 16, wherein, in the second mode, when the first externally received timing reference is inactive, the at least one transition of the second externally received timing reference to be provided received via the signal input.

18. A memory component, comprising: control circuitry to operate the memory component in at least a first mode and a second mode;a signal interface to receive a timing signal;a command/address interface to, based at least in part on the memory component being operated in a first mode, receive first information that is provided to the command/address interface synchronously with a first timing reference signal, the first information including address information sufficient to activate a first row of a first bank of a memory core, the command/address interface to also, based at least in part on the memory component being operated in a second mode, receive second information that is provided to the command/address interface asynchronously to the first timing reference signal and a second timing reference signal, the second information to be sampled from the command/address interface based at least in part on the timing signal; anda data interface to, based at least in part on the memory component being operated in the second mode, receive third information that is provided to the data interface asynchronously to first timing reference signal and the second timing reference signal, the third information to be sampled from the data interface based at least in part on the timing signal, the second information and the third information aggregately including address information sufficient to activate a second row of a second bank of the memory core.

19. The memory component of claim 18, wherein receipt of the second information and the third information is to initiate a self-timed activation of the second row of the second bank of the memory core.

20. The memory component of claim 19, wherein, based on the memory component being operated in the first mode, the signal interface receives a control signal that enables the command/address interface to receive command/address information synchronously with respect to the first timing reference signal and enables the data interface to communicate data synchronously with respect to the second timing reference signal.

21. The memory component of claim 20, wherein during the self-timed activation, the second timing reference signal is to be activated and the data interface is to be enabled to communicate data synchronously.