LOW-POWER-CONSUMPTION LOW-VOLTAGE DIGITAL TEMPERATURE SENSOR

Abstract

A low-power-consumption low-voltage digital temperature sensor, which acquires temperature information by means of the frequency ratio of a first oscillation signal outputted by a first annular oscillator to a second oscillation signal outputted by a second annular oscillator. The first annular oscillator additionally uses an MOS varactor as a load capacitor, and uses the voltage characteristics of the MOS varactor to lower the power supply voltage fluctuation sensitivity, which is suitable for a low-power-consumption low-voltage environment; meanwhile, the sensor has the advantages of a small size, high digitization, self referencing and the like.

Description

FIELD OF THE INVENTION

The invention relates to a low-power-consumption low-voltage temperature sensor, belonging to the field of integrated circuits.

BACKGROUND OF THE INVENTION

Today, processors and Dynamic Random Access Memories (DRAMs) utilize multiple on-chip temperature sensors for thermal monitoring. In the case of a processor, temperature sensors help maintain performance and reliability by monitoring cold and hot spots. On the other hand, the DRAM controls the rate of self-refresh operation according to the current temperature of the chip to save power consumption. Since it is difficult to predict the hot spot locations at the design stage, microprocessors contain as many as ten or more sensors per core. Driven by the ever-increasing computation demand, the number of temperature sensors in a processor will continue to increase as the number of cores per processor per year increases.

Therefore, there is a strong need for a low power, low cost temperature sensor suitable for integration in processors and DRAMs. The sensor must contain several key functions to make it suitable for use in a processor. First, they must be small and compact so that they can be placed very close to the hot spot. Sensors designed to operate using a logic supply voltage help reduce the overhead associated with wiring of a separate dedicated power supply. However, the logic power supply is very noisy due to the constant switching of the logic gates. Furthermore, due to the use of dynamic voltage scaling in modern processors, their average voltage may vary greatly. Therefore, the sensor must be immune to variations in the supply voltage. The SoC and processor also employ a dynamic frequency scaling algorithm, where the switching frequency is scaled to trade off power versus performance. The use of dynamic voltage and frequency scaling algorithms can limit the design of the temperature sensor, making the sensor no longer dependent on using the external frequency or supply voltage as a reference. It is an expensive task to spread the reference frequency, voltage and bias current dedicated to the temperature sensor throughout the processor. Therefore, the temperature sensor must be self-referencing. Finally, the temperature sensor architecture should be relatively easy to design and enable it to be ported to different process nodes.

Currently, several full CMOS based sensor architectures have been proposed to meet the above requirements: thermal diffusivity-based sensors have higher accuracy and smaller area, but their power consumption is higher. The DTMOST-based sensor provides high accuracy, low power consumption and operating voltages below 1V, but occupies a large area.

SUMMARY OF THE INVENTION

The invention aims to provide a low-power-consumption low-voltage digital temperature sensor utilizing the voltage characteristic of a MOS varactor.

The invention adopts the following technical scheme for solving the technical problems: the invention designs a low-power-consumption low-voltage digital temperature sensor, which comprises a first ring oscillator, a second ring oscillator, a first integrator, a second integrator, a D trigger and a linear optimization module, wherein an output end of the first ring oscillator is connected with an input end of the first integrator; an output end of the second ring oscillator is connected with a clock input end of the second integrator, a clock input end of a state machine and a clock input end of the D trigger; an output end of the first integrator is connected with a data input end of the D trigger; an output end of the second integrator is connected with a data input end of the state machine; a first output end of the state machine is connected with a control end of the first integrator; a second output end of the state machine is connected with a control end of the second integrator; and a data output end of the D trigger is connected with an input end of the linear optimization module.

As a preferred technical scheme of the invention: the first ring oscillator comprises N first delay units, wherein N is a positive odd number, the N first delay units are sequentially connected end to end form a closed loop, and an output end of a last first delay unit is used as an output end of the first ring oscillator.

As a preferred technical scheme of the invention: the second ring oscillator comprises M second delay units, wherein M is a positive odd number, the M second delay units are sequentially connected end to end to form a closed loop, and an output end of a last second delay unit is used as an output end of the second ring oscillator.

As a preferred technical scheme of the invention: the first delay unit comprises a first PMOS tube M_P1, a second PMOS transistor M_P2, a first NMOS transistor M_N1 and a first MOM capacitor Can, wherein, a gate of the first PMOS transistor M_P1 is connected with a gate of the first NMOS transistor M_N1 and used as an input end of the first delay unit: a drain of the first PMOS transistor M_P1 is connected with a drain of the first NMOS transistor M_N1, a source of the second PMOS transistor M_P2 and a drain second PMOS transistor a substrate of the second PMOS transistor M_P2 an upper electrode plate of first MOM capacitor C_M1 and used as an output end of the first delay unit; a source of the first PMOS transistor Mm and a gate of the second PMOS transistor M_P2 are connected with power supply voltage; a source of the first NMOS transistor M_N1 and a lower electrode plate of the first MOM capacitor Curare connected to ground.

As a preferred technical scheme of the invention: the second delay unit comprises a third PMOS tube M_P3, a second NMOS transistor M_N2 and a second MOM capacitor C_M2, wherein a gate of the third PMOS transistor M_P3 is connected with a gate of the second NMOS tube M_N2 and used as an input end of the second delay unit; a drain of the third PMOS transistor M_P3 is connected with a drain of the second NMOS tube M_N2 and an upper electrode plate of the second MOM capacitor C_M2 and used as an output end of the second delay unit; a source of the third PMOS transistor M_P3 is connected with a power supply voltage; a source of the second NMOS transistor M_N2 and a lower electrode plate of the second MOM capacitor C_M2 are connected to ground.

Compared with the prior art, the low-power-consumption low-voltage digital temperature sensor has the following technical effects: the invention relates to the low-power-consumption low-voltage digital temperature sensor, which is characterized in that temperature information is obtained through the frequency ratio of a first oscillation signal output by the first ring oscillator to a second oscillation signal output by the second ring oscillator, the two ring oscillators are designed to have different temperature sensitivities, the first integrator and the second integrator respectively integrate the phases of the first oscillation signal and the second oscillation signal, the state machine controls the integrators to reset and freeze, when the integration result of the second integrator reaches a threshold value, the integration result of the first integrator is frozen and output, the D trigger samples by taking the second oscillation signal as a clock to obtain the temperature information, the first ring oscillator additionally adopts the MOS varactor as a load capacitor, the voltage fluctuation sensitivity is reduced by utilizing the voltage characteristic of the varactor, and the sensor has low power consumption and small size, high digitalization, self-reference and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the main circuit of the low power consumption low voltage digital temperature sensor designed by the present invention;

FIG. 2 is a schematic diagram of a circuit configuration of the first ring oscillator designed by the present invention;

FIG. 3 is a schematic diagram of the circuit configuration of the second ring oscillator designed by the present invention;

FIG. 4 shows theory and simulation of low voltage fluctuation sensitivity designed by the present invention.

DETAILED DESCRIPTION

The following description will explain embodiments of the present invention in further detail with reference to the accompanying drawings.

As shown in FIG. 1, the low power consumption and low voltage digital temperature sensor designed by the present invention comprises a first ring oscillator, a second ring oscillator, a first integrator, a second integrator, a D trigger and a linear optimization module, wherein an output end of the first ring oscillator is connected with an input end of the first integrator; an output end of the second ring oscillator is connected with a clock input end of the second integrator, a clock input end of a state machine and a clock input end of the D trigger; an output end of the first integrator is connected with a data input end of the D trigger; an output end of the second integrator is connected with a data input end of the state machine; a first output end of the state machine is connected with a control end of the first integrator; a second output end of the state machine is connected with a control end of the second integrator; and a data output end of the D trigger is connected with an input end of the linear optimization module.

As shown in FIG. 2, the first ring oscillator comprises N first delay units, wherein N is a positive odd number, the N first delay units are sequentially connected end to end form a closed loop, and an output end of a last first delay unit is used as an output end of the first ring oscillator.

In the practical application process of the low-power-consumption low-voltage digital temperature sensor, the first delay unit is specifically designed, as shown in FIG. 2 and comprises a first PMOS tube M_P1, a second PMOS transistor M_P2, a first NMOS transistor MM and a first MOM capacitor Cui wherein, a gate of the first PMOS transistor M_N1 is connected with a gate of the first NMOS transistor M_N1 and used as an input end of the first delay unit; a drain of the first PMOS transistor M_N1 is connected with a drain of the first NMOS transistor M_N1, a source of the second PMOS transistor M_P2 and a drain second PMOS transistor a substrate of the second PMOS transistor M_P2 an upper electrode plate of first MOM capacitor C_M1 and used as an output end of the first delay unit; a source of the first PMOS transistor M_P1 and a gate of the second PMOS transistor M_P2 are connected with power supply voltage; a source of the first NMOS transistor M_N1 and a lower electrode plate of the first MOM capacitor C_M1 are connected to ground.

As shown in FIG. 3, the second ring oscillator comprises M second delay units, wherein M is a positive odd number, the M second delay units are sequentially connected end to end to form a closed loop, and an output end of a last second delay unit is used as an output end of the second ring oscillator.

In the practical application process of the low-power-consumption low-voltage digital temperature sensor, the second delay unit is specifically designed as shown in FIG. 3, and comprises a third PMOS tube M_P3, a second NMOS transistor M_N2 and a second MOM capacitor C_M2, wherein a gate of the third PMOS transistor MP3 is connected with a gate of the second NMOS tube M_N2 and used as an input end of the second delay unit; a drain of the third PMOS transistor M_P3 is connected with a drain of the second NMOS tube M_N2 and an upper electrode plate of the second MOM capacitor C_M2 and used as an output end of the second delay unit; a source of the third PMOS transistor M_P3 is connected with a power supply voltage; a source of the second NMOS transistor M_N2 and a lower electrode plate of the second MOM capacitor C_M2 are connected to ground.

The first order equation for the frequency ratio of the first oscillation signal to the second oscillation signal, F_RO1/F_RO2, can be written as:

$\frac{F_{RO1}}{F_{\mathrm{RO}2}}\propto \frac{{\left(V_{\mathrm{DD}}-V_{\mathrm{TH}1}\right)}^{\alpha }}{{\left(V_{\mathrm{DD}}-V_{\mathrm{TH}2}\right)}^{\alpha }}\frac{C_{M2}}{C_{M1}+C_T},$

• • where V_DD is the power supply voltage, V_TH1 and V_TH2 are the threshold voltage of MOS transistors in the first and second ring oscillators, C_T is equivalent capacitance of the a second PMOS transistor M_P2, α is a model of α power law, α ˜1. As the threshold voltage of the first ring oscillator V_TH1 is designed to be higher than the threshold voltage of the second ring oscillator V_TH2 for ΔV_TH, the above formula can be simplified as:

$\frac{F_{RO1}}{F_{\mathrm{RO}2}}\propto {\left(1-\frac{\Delta V_{\mathrm{TH}}}{V_{\mathrm{DD}}-V_{\mathrm{TH}}}\right)}^{\alpha }\frac{C_{M2}}{C_{M1}+C_T}.$

As shown in FIG. 4(a), the above formula consists of two terms. The first term has positive sensitivity to supply voltage, the second term is C_M2/(C_M1+C_T).

In the present invention, the first ring oscillator additionally adopts a MOS varactor as a load capacitor, and utilizes the voltage characteristic of the MOS varactor, when V_DD is increased, the first MOM capacitor C_M1 and the second MOM capacitor C_M2 are unchanged, while equivalent capacitance C_T of the second PMOS transistor M_P2 becomes larger, as shown in FIG. 4(b), the second term has a negative sensitivity to the supply voltage. As shown in FIG. 4(c), the result of the combination of the first term and the second term makes the frequency ratio achieve lower voltage fluctuation sensitivity.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims

1. A low-power-consumption low-voltage digital temperature sensor, characterized in that: comprising a first ring oscillator, a second ring oscillator, a first integrator, a second integrator, a D trigger and a linear optimization module, wherein an output end of the first ring oscillator is connected with an input end of the first integrator; an output end of the second ring oscillator is connected with a clock input end of the second integrator, a clock input end of a state machine and a clock input end of the D trigger; an output end of the first integrator is connected with a data input end of the D trigger; an output end of the second integrator is connected with a data input end of the state machine; a first output end of the state machine is connected with a control end of the first integrator; a second output end of the state machine is connected with a control end of the second integrator; and a data output end of the D trigger is connected with an input end of the linear optimization module.

2. The low-power-consumption low-voltage digital temperature sensor of claim 1, characterized in that: the first ring oscillator comprises N first delay units, wherein N is a positive odd number, the N first delay units are sequentially connected end to end form a closed loop, and an output end of a last first delay unit is used as an output end of the first ring oscillator.

3. The low-power-consumption low-voltage digital temperature sensor of claim 2, characterized in that: the first delay unit comprises a first PMOS tube MP1, a second PMOS transistor MP2, a first NMOS transistor MN1 and a first MOM capacitor CM1, wherein, a gate of the first PMOS transistor MP1 is connected with a gate of the first NMOS transistor MM1 and used as an input end of the first delay unit: a drain of the first PMOS transistor MP1 is connected with a drain of the first NMOS transistor MN1, a source of the second PMOS transistor MP2 and a drain second PMOS transistor a substrate of the second PMOS transistor MP2 an upper electrode plate of first MOM capacitor CM1 and used as an output end of the first delay unit; a source of the first PMOS transistor MP1 and a gate of the second PMOS transistor MP2 are connected with power supply voltage; a source of the first NMOS transistor MN1 and a lower electrode plate of the first MOM capacitor CM1 are connected to ground.

4. The low-power-consumption low-voltage digital temperature sensor of claim 1, characterized in that: the second ring oscillator comprises M second delay units, wherein M is a positive odd number, the M second delay units are sequentially connected end to end to form a closed loop, and an output end of a last second delay unit is used as an output end of the second ring oscillator.

5. The low-power-consumption low-voltage digital temperature sensor of claim 4, characterized in that: the second delay unit comprises a third PMOS tube MP3, a second NMOS transistor MN2 and a second MOM capacitor CM2, wherein a gate of the third PMOS transistor MP3 is connected with a gate of the second NMOS tube MN2 and used as an input end of the second delay unit; a drain of the third PMOS transistor MP3 is connected with a drain of the second NMOS tube MN2 and an upper electrode plate of the second MOM capacitor CM2 and used as an output end of the second delay unit; a source of the third PMOS transistor MP3 is connected with a power supply voltage; a source of the second NMOS transistor MN2 and a lower electrode plate of the second MOM capacitor CM2 are connected to ground.