Low swing domino logic circuits

Abstract

Low voltage swing techniques are provided for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. One or both the upper and lower boundaries of the voltage swing at the dynamic node may be different from the upper and lower boundaries of the voltage swing at the output node. For example, the voltage swing at the dynamic node may be less than the voltage swing at the output node, optimized for speed or power consumption. As another example, the voltage swing at the dynamic node may be greater than the voltage swing at the output node, optimized for speed or power consumption. Further, the domino logic circuit may use dual Vt thereby reducing the short-circuit current during operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The system may be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the figures, like referenced numerals designate corresponding parts throughout the different views.

FIG. 1 is a schematic of one example of a prior art domino logic circuit.

FIG. 2 is a schematic of another example of a prior art domino logic circuit.

FIG. 3 is a schematic of yet another example of a prior art domino logic circuit.

FIG. 4 is a schematic of a footless bidirectional dynamic node low voltage swing domino logic circuit with dual power supplies and ground voltages where one or more of the power supplies may be optimized.

FIG. 5 is a schematic of a footed bidirectional dynamic node low voltage swing domino logic circuit with dual power supplies and ground voltages where one or more of the power supplies may be optimized.

FIG. 6 is another example of a schematic of a footless bidirectional dynamic node low voltage swing domino logic circuit with dual power supplies and ground voltages where one or more of the power supplies may be optimized.

FIG. 7 is another example of a schematic of a footed bidirectional dynamic node low voltage swing domino logic circuit with dual power supplies and ground voltages where one or more of the power supplies may be optimized.

FIG. 8 is a schematic of a footless bidirectional dynamic node low voltage swing domino logic circuit with dual power supplies and ground voltages without a keeper circuit and where one or more of the power supplies may be optimized.

FIG. 9 is a schematic of a footed bidirectional dynamic node low voltage swing domino logic circuit with dual power supplies and ground voltages without a keeper circuit and where one or more of the power supplies may be optimized.

FIG. 10 is a schematic of a footless bidirectional dynamic node low voltage swing domino logic circuit with one power supply and two ground voltages where one or more of the power supplies may be optimized.

FIG. 11 is a schematic of a footed bidirectional dynamic node low voltage swing domino logic circuit with one power supply and two ground voltages where one or more of the power supplies may be optimized.

FIG. 12 is a schematic of a low swing buffer with a standard power supply and ground voltages and V_DDL=V_DD−V_tn.

FIG. 13 is another example of a schematic of a footless bidirectional dynamic node low voltage swing domino logic circuit with one power supply and two ground voltages where one or more of the power supplies may be optimized.

FIG. 14 is another example of a schematic of a footed bidirectional dynamic node low voltage swing domino logic circuit with one power supply and two ground voltages where one or more of the power supplies may be optimized.

FIG. 15 is a schematic of a footless bidirectional dynamic node low voltage swing domino logic circuit with one power supply and two ground voltages, without a keeper circuit, and where one or more of the power supplies may be optimized.

FIG. 16 is a schematic of a footed bidirectional dynamic node low voltage swing domino logic circuit with one power supply and two ground voltages, without a keeper circuit, and where one or more of the power supplies may be optimized.

FIG. 17 is a schematic of a footless bidirectional dynamic node low voltage swing domino logic circuit with one power supply and two ground voltages, with a sleep transistor, and where one or more of the power supplies may be optimized.

FIG. 18 is another example of a schematic of a footless bidirectional dynamic node low voltage swing domino logic circuit with one power supply and two ground voltages, with a sleep transistor, and where one or more of the power supplies may be optimized.

FIG. 19 is still another example of a schematic of a footless bidirectional dynamic node low voltage swing domino logic circuit with one power supply and two ground voltages, without a keeper circuit, with a sleep transistor, and where one or more of the power supplies may be optimized.

FIG. 20 depicts a schematic of a footless output low voltage swing domino logic circuit with dual power supplies, where the output is low-swing.

FIG. 21 depicts another schematic of a footed output low voltage swing domino logic circuit with dual power supplies, where the output is low-swing.

FIG. 22 depicts yet another schematic of a footed output low voltage swing domino logic circuit with dual power supplies, where the output is low-swing.

FIG. 23 is a schematic of a bidirectional dynamic node low voltage swing multiple threshold voltage domino circuit with dual power supply and ground voltages.

FIG. 24 is another schematic of a bidirectional dynamic node low voltage swing multiple threshold voltage domino circuit with dual power supply and ground voltages.

FIG. 25 is yet another schematic of a bidirectional dynamic node low voltage swing multiple threshold voltage domino circuit with dual power supply and ground voltages.

FIG. 26 is a schematic of a bidirectional dynamic node low voltage swing multiple threshold voltage domino circuit with single power supply and dual ground voltages.

FIG. 27 is a schematic of a bidirectional dynamic node low voltage swing multiple threshold voltage domino circuit with dual power supply and ground voltages.

FIG. 28 is a schematic of a bidirectional dynamic node low voltage swing multiple threshold voltage domino circuit with single power supply and dual ground voltages.

FIG. 29 is a schematic of a body biased bidirectional dynamic node low voltage swing domino circuit with dual power supply and ground voltages.

FIG. 30 is a schematic of a body biased bidirectional dynamic node low voltage swing domino circuit with dual power supply and ground voltages.

FIG. 31 is a schematic of a dynamic node low voltage swing multiple threshold voltage domino circuit with single power supply and ground voltage.

FIG. 32 is a schematic of a dynamic node low voltage swing multiple threshold voltage domino circuit with single power supply and ground voltage.

FIG. 33 is a schematic of a body biased low swing multiple threshold voltage domino circuit with single power supply and ground voltage.

FIG. 34 is a schematic of a body biased low swing domino circuit with single power supply and ground voltage.

Claims

1. A domino logic circuit comprising: a precharge circuit for precharging a dynamic node to a predetermined value;an input circuit having at least one input and at least one output, the at least one output in communication with the dynamic node, the input circuit comprising logic for determining a value of the dynamic node based on the at least one input;an output circuit having at least one input and at least one output, the at least one input in communication with the dynamic node; andwherein a voltage swing at the dynamic node is different from a voltage swing at the output for the output circuit, andwherein at least one transistor in the precharge circuit or the output circuit has a higher threshold voltage than at least some of the transistors in the input circuit in order to reduce short-circuit current.

2. The domino logic circuit of claim 1, wherein the voltage swing at the dynamic node is less than the voltage swing at the output for the output circuit.

3. The domino logic circuit of claim 2, wherein the output circuit comprises an inverter; and wherein at least one of the transistors in the inverter has a higher threshold voltage.

4. The domino logic circuit of claim 3, wherein only one of the transistors in the inverter has a higher threshold voltage.

5. The domino logic circuit of claim 2, wherein the precharge circuit comprises a pull-up transistor; and wherein the pull-up transistor has a higher threshold voltage.

6. The domino logic circuit of claim 2, further comprising a keeper circuit for keeping the dynamic node at the predetermined value after the precharge circuit precharges the dynamic node to the predetermined value; and wherein at least one of the transistors in the keeper circuit has a higher threshold than the transistors in the input circuit.

7. The domino logic circuit of claim 6, wherein the keeper circuit comprises a plurality of transistors; and wherein fewer than all of the plurality of transistors has a higher threshold than the transistors in the input circuit.

8. The domino logic circuit of claim 1, wherein the at least one transistor is body biased in order to produce the higher threshold voltage.

9. The domino logic circuit of claim 1, wherein the at least one transistor has a different construction than the at least some of the transistors in the input circuit in order to produce the higher threshold voltage in the at least one transistor.

10. A domino logic circuit comprising: a precharge circuit for precharging a dynamic node to a predetermined value;an input circuit having at least one input and at least one output, the at least one output in communication with the dynamic node, the input circuit comprising logic for determining a value of the dynamic node based on the at least one input;an output circuit having at least one input and at least one output, the at least one input in communication with the dynamic node; andwherein a voltage swing at the dynamic node is greater than a voltage swing at the output for the output circuit.

11. The domino logic circuit of claim 10, wherein the domino logic circuit comprises at least two power supplies, the power supply to the output circuit being a lower voltage than the power supply to the precharge circuit.

12. The domino logic circuit of claim 10, wherein the domino logic circuit comprises at least two ground voltages, the ground voltage to the output circuit being a greater voltage than the ground voltage to the input circuit.

13. The domino logic circuit of claim 10, wherein the domino logic circuit comprises at least two power supplies, the power supply to the output circuit being a lower voltage than the power supply to the precharge circuit; and wherein the domino logic circuit comprises at least two ground voltages, the ground voltage to the output circuit being a greater voltage than the ground voltage to the input circuit.

14. The domino logic circuit of claim 10, further comprising a keeper circuit for keeping the dynamic node at the predetermined value after the precharge circuit precharges the dynamic node to the predetermined value; and wherein power for the keeper circuit comprises the power supply to the precharge circuit and ground for the keeper circuit comprises the ground voltage to the input circuit.

15. A domino logic circuit comprising: a precharge circuit for precharging a dynamic node to a predetermined value;an input circuit having at least one input and at least one output, the at least one output in communication with the dynamic node, the input circuit comprising logic for determining a value of the dynamic node based on the at least one input;an output circuit having at least one input and at least one output, the at least one input in communication with the dynamic node; andwherein a voltage swing at the dynamic node is less than and asymmetrical to a voltage swing at the output for the output circuit.

16. The domino logic circuit of claim 15, wherein the voltage swing at the dynamic mode is optimized for speed of the domino logic circuit.

17. The domino logic circuit of claim 15, wherein the voltage swing at the dynamic mode is optimized for lower power consumption of the domino logic circuit.

18. The domino logic circuit of claim 15, wherein the voltage swing at the dynamic node comprises a dynamic node high voltage and a dynamic node low voltage; wherein the voltage swing at the output node comprises an output node high voltage and an output node low voltage; andwherein at least one of the dynamic node high voltage and the dynamic node low voltage is different from the output node high voltage and the output node low voltage.

19. The domino logic circuit of claim 18, wherein the dynamic node high voltage is less than the output node high voltage; and wherein the dynamic node low voltage is greater than the output node low voltage.

20. The domino logic circuit of claim 19, wherein a difference between the output node high voltage and dynamic node high voltage is greater than a difference between the dynamic node low voltage and output node low voltage.

21. The domino logic circuit of claim 20, wherein the domino logic circuit comprises at least two power supplies and at least two ground voltages.