Patent Application
20170186935
When a silicon containing structure is formed over a metal structure, a barrier layer is often used to prevent silicide formation at the interface of the silicon containing structure and the metal structure. For example, a barrier layer may be used when a silicon-containing low loss dielectric (LLD) layer, such as an amorphous silicon or silicon oxide, is formed over a metal electrode in a superconducting circuit. Without a barrier layer, there is a direct contact between metal and silicon atoms and silicides can start forming when the temperature exceeds 500° C. for most common metals. Formation of silicides may be undesirable because it leads to poor loss in superconducting (radio frequency) RF circuits, for example. While forming barrier layers adds to processing time and costs and may be not possible in some application, lowering deposition temperatures is generally not possible for most conventional silicon precursors, such as mono-silane.
Provided are superconducting circuits and, more specifically, methods of forming such circuits. A method may involve forming a silicon-containing LLD layer over a metal electrode such that metal carbides at the interface of the LLD layer and electrode. The LLD layer may be formed using chemical vapor deposition (CVD) at a temperature of less than about 500° C. At such a low temperature, metal silicides may not form even though silicon containing precursors may come in contact with metal of the electrode. Silicon containing precursors having silane molecules in which two silicon atoms bonded to each other (e.g., di-silane and tri-silane) may be used at these low temperatures. The LLD layer may include amorphous silicon, silicon oxide, or silicon nitride, and this layer may directly interface one or more metal electrodes. The thickness of the LLD layer may be between about 1,000 Angstroms and 10,000 Angstroms.
In some embodiments, a method of forming a superconducting circuit involves providing a metal layer. The metal layer may be a part of a Josephson junction, for example. The method continues with forming an LLD layer over the metal layer using CVD. The metal layer is kept at a temperature below about 525° C. while forming the LLD layer. The LLD layer includes one of amorphous silicon, silicon oxide, or silicon nitride. The dielectric layer is formed using a silicon containing precursor. For example, the silicon containing precursor may include silane molecules in which two silicon atoms bonded to each other, such as di-silane or tri-silane. Without being restricted to any particular theory, it is believed that having one or more silicon-silicon bonds in the silicon containing precursor allows using lower deposition temperatures than, for example, when a silane is used. In some embodiments, the silane molecules of the silicon containing precursor have no silicon atoms each bonded with three or more other silicon atoms, such as in a higher level poly-silane.
In some embodiments, the LLD layer directly interfaces the metal layer. The interface between the metal layer and the LLD layer may be substantially free of a metal silicide. The lack of metal silicides at the interface may be attributed to low deposition temperatures. In some embodiments, the metal layer includes one of niobium or aluminum. The LLD layer may include amorphous silicon or silicon oxide.
In some embodiments, the chemical vapor deposition used to form the LLD layer is plasma enhanced chemical vapor deposition (PECVD). The metal layer may be kept at the temperature below about 500° C. while forming the LLD layer. More specifically, the metal layer may be kept at the temperature between about 475° C. and 500° C. while forming the LLD layer.
In some embodiments, providing the metal layer involves forming the metal layer using physical vapor deposition (PVD). Forming of the metal layer and forming the LLD layer may be performed in situ, for example. The LLD layer may have a thickness of between about 1,000 Angstroms and 10,000 Angstroms.
These and other embodiments are described further below with reference to the figures.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented concepts. The presented concepts may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail so as to not unnecessarily obscure the described concepts. While some concepts will be described in conjunction with the specific embodiments, it will be understood that these embodiments are not intended to be limiting.
Typically, integrated circuits combine multiple layers, including conductive, semi-conductive and/or insulating layers. For example, superconducting devices, such as Josephson junctions, include two metal electrodes separated by a thin insulating dielectric. Integrated circuits may be a part of larger, multilayer devices to serve a particular purpose. For example, Josephson junctions can be used in superconducting quantum interference devices (SQUIDs), superconducting tunnel junction detectors (STJs), Rapid Single Flux Quantum (RSFQ) devices, single-electron transistors, and other applications. In some embodiments, integrated circuits use insulating layers, including silicon-containing insulating layers, such as LLD layers, to electrically insulate metal electrodes and provide additional strength to the device. However, it can be challenging to create silicon-containing LLD layers without forming silicide.
Silicide formation at an interface of a silicon-containing structure and a metal structure is undesirable in many applications, such as superconducting circuits, when a silicon-containing LLD layer is formed over a metal electrode, for example. The silicon-containing LLD layer and other similar structures are often formed using CVD, during which a silicon containing precursor is flown into a deposition chamber. The silicon containing precursor either decomposes or reacts with another gas at a deposition surface maintained at an elevated temperature. Initially, the deposition surface may be an exposed surface of the metal structure when, for example, a barrier layer is not used. Considering that the silicon containing precursor needs to be a highly reactive substrates and that deposition needs to be performed at a higher temperature, the silicon containing precursor may also react with metal of the deposition surface thereby forming silicides.
The silicon-containing precursor most commonly used for growing amorphous silicon and silicon oxide is mono-silane (SiH4). When amorphous silicon is grown on niobium using mono-silane (SiH4), the deposition temperature may need to be about 550° C. to achieve any reasonable deposition rate. At 550° C. (and above), silicides readily form on surfaces of many superconducting metal electrodes, such as elemental niobium electrode and elemental titanium electrode. In other words, at a temperature of 550° C. and above, mono-silane (SiH4) will react with niobium and/or tantalum and quickly form silicide while a silicon containing layer is being deposited directly on the superconducting metal electrode. Formation of silicides at an interface of an LLD later and electrode is not desirable as its leads to poor loss in the superconducting circuit. In many superconducting circuits the dielectric layer is used to form RF micro-strips. The loss at cryogenic temperatures in these micro-strips can be dominated by loss in the dielectric. The mechanism for this loss is known to be from two-level system fluctuations from defects such as dangling bonds. One having ordinary skills in the art would understand that, silicides are known to produce a large amount of these two-level system defects and create substantial loss.
It has been found that amorphous silicon can be grown over a niobium structure (e.g., an LLD formed over a niobium electrode) using tri-silane (Si3H8) as a precursor instead of mono-silane (SiH4). As a result of replacing mono-silane (SiH4) with tri-silane (Si3H8), the deposition temperature can be lowered from 550° C. to 515° C. or even down to about 425° C. A combination of tri-silane (Si3H8) and a lower deposition temperature led to effectively no silane formed at the interface of amorphous silicon and niobium structure. X-ray photoelectron spectroscopy (XPS) analysis of amorphous silicon samples formed on niobium surfaces formed using tri-silane (Si3H8) at a lower temperature of 515° C. showed no evidence of niobium-silicide. Furthermore, the quality of amorphous silicon produced using tri-silane (Si3H8) at a lower temperature of 515° C. is at least as good or, in some instances, even better than that produced using mono-silane (SiH4) at from 550° C. Specifically, a high electron spin resonance (ESR) signal correlates with high loss, while a low ESR correlates with low loss. The ESR signal corresponding to a sample formed using tri-silane (Si3H8) at a lower temperature of 515° C. was actually lower than that corresponding to a sample formed mono-silane (SiH4) at from 550° C. In other words, using tri-silane (Si3H8) and lowering the deposition temperature of 515° C. effectively eliminated silicides at the interface and substantially reduced the loss.
Atomic Layer Deposition (ALD), CVD, Electron Beam Physical Vapor Deposition (EBPVD), Pulsed Laser Deposition (PLD), evaporative deposition, cathodic arc deposition, thermal spray coating, sputter deposition, electroplating, photolitography, and so forth. Suitable methods for selective etching of the conductive layers include, but not limited to, wet etching, anisotropic wet etching, plasma etching, dry etching, reactive ion etching (RIE), hydrofluoric acid or buffered oxide etchant (BOE) etching.
In superconducting microwave devices, electrodes 102A or vias 112A may be any suitable superconducting material, such as aluminum (Al), aluminum alloys, aluminum nitrides, niobium (Nb), niobium alloys, niobium nitrides, ceramic superconductors, or organic superconductors. Substrate 101A may include a silicon or silicon oxide layer. In some embodiments, substrate 101A can be a part of a wafer, die, or integrated circuit.
The illustrated structures also include electrical components 104 such as discrete or embedded transistors, capacitors, switches, resistors, resonators. In superconducting embodiments, components 104 may include Josephson junctions. In some embodiments, electrodes 102B are parts of Josephson junctions. For example, Josephson junctions may include electrode 102B interfacing with a thin dielectric layer to exhibit superconducting properties. Electrode 102B can include a metal, such as niobium or aluminum, nitrides thereof, alloys, or another suitable material. Electrodes 102B have a thickness of between about 1500A and 3000A or, more specifically, between about 1500A and 3000A. In some embodiments, the thickness is greater than a so called the London penetration depth, which for niobium is about 1200A. There may be no upper bound on the thickness from the device performance perspective. However, the upper bound may be established by device packaging and other considerations. The thin dielectric layer may include aluminum oxide. Other examples of suitable dielectric materials include but not limited to, magnesium oxide, lanthanum oxide, and other metal oxides. In some embodiments, the thin dielectric layer has a thickness of between about 5 Angstroms and 50 Angstroms or, more specifically, between about 10 Angstroms and 30 Angstroms.
The shape and dimensions of the first metal layer may vary depending on an application. In one example, the first metal layer may include a metal stripe. In another example, the first metal layer may be selectively patterned and include one or more turns. In yet more embodiments, the first metal layer may be combined with or include interconnect structures, such as vias 112A and 112B shown in
The first metal layer can be fabricated using a wide range of deposition and patternmaking methods. Some suitable methods for depositing the first metal layer include, but not limited to, PVD, ALD, CVD, EBPVD, PLD, evaporative deposition, cathodic arc deposition, thermal spray coating, sputter deposition, electroplating, photolitography, and so forth. Suitable methods for selective patterning of the first metal layer include, but not limited to, wet etching, anisotropic wet etching, plasma etching, dry etching, RIE, hydrofluoric acid or BOE etching.
Still referring to
The LLD layer can be fabricated from a precursor using, for example, CVD process, although other deposition methods can be also used. Particularly, the first metal layer is kept at a temperature below about 525° C. while forming the LLD layer. The LLD layer includes one of amorphous silicon, silicon oxide, or silicon nitride. The precursor can include a silicon-containing material including silane molecules. For example, the silicon containing precursor may include silane molecules in which two silicon atoms bonded to each other forming di-silane or tri-silane. In other embodiments, the silicon-containing precursor can include a combination of tri-silane and di-silane. The ratio of tri-silane to di-silane in the precursor can be predetermined and be in a range from about 1:1 to about 100:1. Without being restricted to any particular theory, it is believed that having one or more silicon-silicon bonds in the silicon containing precursor allows using lower deposition temperatures than, for example, when a silane is used. In some embodiments, the silane molecules of the silicon-containing precursor have no silicon atoms each bonded with three or more other silicon atoms, such as in a higher level poly-silane.
In some embodiments, the LLD layer directly interfaces the first metal layer. The interface between the first metal layer and the LLD layer may be substantially free of a metal silicide. The lack of metal silicides at the interface may be attributed to low deposition temperatures. For purposes of this disclosure, the term “substantially” used in the context of the lack of metal silicide molecules within the LLD layer or the interface between the LLD layer and the first metal layer shall mean that the level of metal silicide molecules in these layers does not negatively affect any operating characteristics of the superconducting circuit. For example, the term “substantially” in this context can mean that there are no more than 10% of metal silicide molecules in the LLD layer or within the interface between the LLD layer and the first metal layer.
In some embodiments, the CVD method used to form the LLD layer is plasma enhanced chemical vapor deposition (PECVD). The metal layer may be kept at the temperature below about 500° C. while forming the LLD layer. More specifically, the first metal layer may be kept at the temperature between about 475° C. and 500° C. while forming the LLD layer. In some embodiments, providing the metal layer involves forming the metal layer using PVD process. Forming of the metal layer and forming the LLD layer may be performed in situ, for example.
Multiple experiments have been conducted to determine how a tri-silane precursor allows creating a LLD layer over a metal layer without forming metal silicides. Particularly,
In all experiments, the substrate included a silicon oxide substrate with the thickness of about 1,000 Angstroms. Further, in all experiments, the niobium film had the thickness of about 500 Angstroms. In the first and second superconducting circuits (i.e., represented by graphs 304 and 306), the LLD layer included amorphous silicon and the thickness of the LLD layer was about 150 Angstroms.
As can be seen from
Although the foregoing concepts have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatuses.
Accordingly, the present embodiments are to be considered as illustrative and not restrictive.
