Patent Application
20130294161
The present invention is generally related with a novel design of static random-access memory (SRAM)-based non-volatile random-access memory (NVRAM) cell structure and array for an extremely fast write (program and erase) speed but low write and read voltage, for an extremely high-density, in-circuit or in-system programmable and erasable field-programmable gate array (FPGA) and NVRAM designs.
The LV SRAM-based FPGA is well known in the art. It is leading in the FPGA market place over today's HV Flash-based FPGA design. The LV SRAM-based FPGA cell and design achieves the highest cell's scalability down to 2×nm in 2012, while the most advanced HV Flash-based FPGA cell and technology node is only at 65 nm.
But there are several severe drawbacks of the today's SRAM-based FPGA cell and its associated designs when memory density requirement is getting higher and higher up to 1 Gb for those very sophisticated configurable logic design. These drawbacks include the followings:
Currently, the mainstream FPGA designs in 2012 are being divided into two groups with two distinct technologies. The first group is the LV SRAM-based FPGA design which leads the market. These LV SRAM-based FPGA companies include Altera, Xilink and many other smaller players. The second group is the HV NVM-based FPGA design, which grabs much smaller market revenues. These NVM-based FPGA companies include Actel, Lattice and the smaller part of Altera.
Some other approaches different from above two distinct designs may have both LV SRAM cells and HV Flash cells on 1-die, they also have other drawbacks. For example, the on-chip Flash memory is used to store the total configuration bits in one or few central memory array areas. During the Vdd power-up, the stored configuration bits on on-chip Flash memory needs to be down complicatedly loaded into the on-chip distributed SRAM cells sequentially with huge time and power consuming. The on-chip state-machine design becomes very difficult and challenging.
The worst-case concern is that when a sudden unexpected Vdd power loss, the huge on-chip SRAM data bits of 200 Mb cannot be safely written into the on-chip huge Flash memory within a period as short as 10 ms by the sudden power-loss without a costly battery back-up. Although there are many Flash memories available in 2012, most of them have different kinds of drawbacks and are not suitable for the SRAM-based NVRAM cell design to directly meet the above said design requirements without the modifications.
Therefore, an improved SRAM-based NVRAM cell design and their associated operations are needed and become objectives of the present invention.
The present invention is generally related with a novel design of static random-access memory (SRAM)-based non-volatile random-access memory (NVRAM) cell structure and array for an extremely fast write (Program and Erase) speed but low Write and Read voltage, for an extremely high-density, in-circuit or in-system programmable and erasable field-programmable gate array (FPGA) and NVRAM designs.
The objectives for this invention of novel NVSRAM cell and its associated controls can be divided into two groups. One group's objective is for traditional FPGA, the other group's objective is for the traditional NVRAM applications. But the goal is to use one NVSRAM cell for both FPGA and NVRAM applications, thus there are some common objectives for both applications. From our study, the preferred Flash cell structures and their associated operations have to meet the following specs:
An objective of this invention is to provide a novel 16T SRAM-based NVSRAM cell structure that comprises 1-bit of 6T-SRAM-based FPGA cell along with 1-bit of a paired Flash strings stored with two complementary Vts. Each Flash string consists of three transistors (3T) with one 2-poly floating-gate flash cell or 1-poly SONOS charge-trapping flash cell and two other 1-poly NMOS devices.
Another objective of this invention is to provide a novel method to increase the Flash cell's word line (WL) coupling ratio of the NVSRAM cell so that Flash cells can be erased and programmed with low-current FN-tunneling scheme at lower WL voltage with respect to 0V set in Flash cell's channel. As a result, the on-chip charge-pump size, power consumption, and write time can be drastically reduced when the NVSRAM cell is operating at 1.2V Vdd.
Further, another object of this invention is to make the equivalent pull-down resistance of each long Flash string lower than the PMOS pull-up resistance of each corresponding SRAM cell with sufficient margin to allow the quick and safe data loading from each Flash cell into each SRAM cell of each NVSRAM cell, operating at low 1.2V Vdd.
Even further, another object of this invention is to gate each paired inputs of each Flash cell input to both Q and QB data nodes of each SRAM cell of each NVSRAM cell so that the data writing from each SRAM loads into each Flash cell via one direct route and the data loads from each Flash cell into each SRAM cell through an opposite route. As a result, the reversed polarity of each Flash cell's writing data can be reversely loaded into each corresponding SRAM cell for correct data reading.
Yet another objective of this invention is to provide one preferred set of Erase bias conditions to allow −12V or lower Flash cell's negative WL voltage to achieve the successful FN-channel tunneling effect on each 2-poly Flash cell of each NVSRAM cell.
Still yet another objective of this invention is to provide another preferred set of Erase bias conditions with enhancing FN-tunneling electrical field so that the required erase time for each 2-poly floating-gate Flash cell of each NVSRAM cell can be shortened.
An alternative objective of this invention is to provide one preferred set of Program bias conditions to allow +12V or lower Flash cell's positive WL voltage to achieve the successful FN-channel tunneling effect on each 2-poly floating-gate Flash cell of each NVSRAM cell.
Another alternative objective of this invention is to provide similar preferred set of Erase bias conditions to allow −7V or even lower Flash cell's negative WL voltage to achieve the successful FN-channel tunneling effect on each 1-poly charge-trapping SONOS-type Flash cell of each NVSRAM cell.
Yet another alternative objective of this invention is to provide similar preferred set of Program bias conditions to allow +7V or lower Flash cell's positive WL voltage to achieve the successful FN-channel tunneling effect on each 1-poly charge-trapping SONOS-type Flash cell of each NVSRAM cell.
Still another alternative objective of this invention is to provide a preferred timeline to show how to correctly program each SRAM data into each Flash cell of each NVSRAM cell.
The Flash cell includes both 2-poly floating-gate Flash cell and 1-poly charge-trapping SONOS-type Flash cell.
Yet still another alternative objective of this invention is to provide a preferred timeline to show how to correctly load each Flash cell's data into each corresponding SRAM cell of each NVSRAM cell. The Flash cell includes both 2-poly floating-gate Flash cell and 1-poly charge-trapping SONOS-type Flash cell.
Yet additional alternative objective of this invention is to provide a preferred timeline to show how to correctly erase each Flash cell of each NVSRAM cell. The Flash cell includes both 2-poly floating-gate Flash cell and 1-poly charge-trapping SONOS-type Flash cell.
Still additional alternative objective of this invention is to provide a preferred timeline to show how to correctly read each SRAM cell out from each NVSRAM cell with Flash cells equivalently out of circuit, irrespective of 2-poly floating-gate Flash cell or 1-poly charge-trapping SONOS-type Flash cell.
In a specific embodiment, the present invention provides a 16T NVSRAM memory cell circuit with low-voltage fast-write scheme. The NVSRAM memory cell includes a SRAM cell comprising a first access transistor and a second access transistor sharing a first word line and respectively coupling between a first bit line and a first data node and between a second bit line and a second data node. The first data node and the second data node respectively are coupled to two cross-coupled invertors made by four LV CMOS transistors. Additionally, the NVSRAM memory cell includes a Flash cell comprising a first cell string and a second cell string sharing a common P-sub. The first/second cell string includes a first/second top Select transistor, a first/second Flash transistor, and a first/second bottom Select transistor connected in series. The first and the second top Select transistors are gated commonly by a first select-gate control line and respectively associated with a first drain terminal and a second drain terminal. The first and the second bottom Select transistors are gated commonly by a second select-gate control line and respectively associated with a first source terminal and a second source terminal. The first and the second Flash transistors are gated commonly by a second word line and the first source terminal and the second source terminal are connected together to a flash source line. Moreover, the NVSRAM memory cell includes a Bridge circuit including a first, second, third, and fourth LV NMOS transistor for connecting the first data node and the second data node of the SRAM cell respectively through two cross routes to the first drain terminal and the second drain terminal of the Flash cell. The first and the third LV NMOS transistors are commonly gated by a FSwrite control line and the second and the fourth LV NMOS transistors are commonly gated by a SFwrite control line. The first and the second LV NMOS transistors have a first common drain node connected to the first data node of the SRAM cell. The second and the third LV NMOS transistors have a first common source node connected to the first drain terminal of the Flash cell. The third and the fourth LV NMOS transistors have a second common drain node connected to the second data node of the SRAM cell. The first and the fourth LV NMOS transistors have a second common source node connected to the second drain terminal of the Flash cell. In an embodiment, only one of the FSwrite control line and the SFwrite control line is turned on at a time by coupling to a power supply voltage as low as 1.2 V Vdd for providing a direct route of writing data from the SRAM cell to the Flash cell via a FN tunneling effect by setting only one HV of +12V or lower the second word line and providing an alternate route of loading data from the Flash cell to the SRAM cell by conducting current from the first or second data node to a grounded flash source line so that a reversed polarity of each data from the Flash cell can be reversely loaded into the SRAM cell operating at the power supply voltage as low as 1.2 V Vdd.
In an alternative embodiment, the present invention provides a 14T NVSRAM memory cell circuit with low-voltage fast-write scheme. The NVSRAM memory cell includes a SRAM cell comprising a first access transistor and a second access transistor sharing a first word line and respectively coupling between a first bit line and a first data node and between a second bit line and a second data node. The first data node and the second data node respectively are coupled to two cross-coupled invertors made by four LV CMOS transistors. Additionally, the NVSRAM memory cell includes a Flash cell comprising a first cell string and a second cell string sharing a common P-sub. The first/second cell string includes at least a first/second Flash transistor connected in series to a first/second Select transistor. The first and the second Select transistors are gated commonly by a select-gate control line and respectively associated with a first source terminal and a second source terminal. The first and the second Flash transistors are gated commonly by a second word line. The first source terminal and the second source terminal are connected together to a flash source line. Furthermore, the NVSRAM memory cell includes a Bridge circuit including a first, second, third, and fourth HV NMOS transistor for connecting the first data node and the second data node of the SRAM cell respectively through two cross routes to the first drain terminal and the second drain terminal of the Flash cell. The first and the third HV NMOS transistors are commonly gated by a FSwrite control line and the second and the fourth HV NMOS transistors are commonly gated by a SFwrite control line. The first and the second HV NMOS transistors have a first common drain node connected to the first data node of the SRAM cell. The second and the third HV NMOS transistors have a first common source node connected to the first drain terminal of the Flash cell. The third and the fourth HV NMOS transistors have a second common drain node connected to the second data node of the SRAM cell. The first and the fourth HV NMOS transistors have a second common source node connected to the second drain terminal of the Flash cell. In a specific embodiment, only one of the FSwrite control line and the SFwrite control line is turned on at a time by coupling to a power supply voltage as low as 1.2 V Vdd for providing a direct route of writing data from the SRAM cell to the Flash cell via a FN tunneling effect by setting only one HV of +12V or lower the second word line and providing an alternate route of loading data from the Flash cell to the SRAM cell by conducting current from the first or second data node to a grounded flash source line so that a reversed polarity of each data from the Flash cell can be reversely loaded into the SRAM cell operating at the power supply voltage as low as 1.2V Vdd.
More specifically, this invention is to provide a novel new SRAM-based NVRAM cell structure which is preferably comprised of one regular 6T SRAM CMOS cell and one pair of 4T Flash strings. Although the total number of transistors (T) of the present invention is 14, which may be larger than most of similar prior art, the NVRAM cell structure and biased conditions and array operations have been much simplified to achieve the lower write voltage but faster write speed from the volatile SRAM cell into non-volatile Flash during the normal or unexpected power down mode or from non-volatile Flash data into volatile SRAM cell during normal Vdd power-up, collectively and simultaneously for whole extremely high-density FPGA array with density up to 1 Gb.
During the normal read operation of the 16T (or 14T) NVRAM cell of the present invention, one pair of 3T (or 2T) Flash strings are totally isolated from 6T SRAM cell from electrical circuit point of view. As a result, the preferred Read operation is like the SRAM-based FPGA so that the performance of FPGA is not degraded.
During the write operation from each SRAM cell on Flash pairs in regular or undesired power-off situations, each of one-pair outputs of the SRAM cell provides a paired LV Program (Vss) voltage and Program-Inhibit (Vdd) voltage so that the NVRAM's Flash pairs can be quickly and correctly programmed without reversing the data polarity at 1.2V Vdd operation.
Many benefits can be achieved by applying the embodiments of the present invention. These and other benefits may be described throughout the present specification and more particularly below.
a is a schematic diagram of a 3T Flash string used in a NVSRAM cell of prior art.
b is a cross-sectional diagram of above 3T Flash string circuit used in a NVSRAM cell of prior art.
c is a schematic diagram of a NVSRAM cell of prior art.
d is a table that provides a set of bias conditions for various key NVSRAM operations such as Erase and Program and Program-Inhibit of the Flash cell and Read of the SRAM cell of the NVSAM cell of prior art.
a is another schematic diagram of a 3T Flash string used in another NVSRAM cell of prior art.
b is a similar cross-sectional diagram of above 3T 1-poly charge-trapping type Flash string circuit used in a NVSRAM cell of prior art of
c is a schematic diagram of another NVSRAM cell of prior art.
d is a table that provides another set of bias conditions for various key NVSRAM operations of
a is a schematic diagram of a 16T 2-poly NVSRAM cell according to an embodiment of the present invention.
b is a table that provides a preferred set of bias conditions for various key NVSRAM operations according to an embodiment of the present invention.
c is a timeline for operating the 3T Flash string of the 16T 2-poly NVSRAM cell according to an embodiment of the present invention.
a is a schematic diagram of a 14T 2-poly NVSRAM cell according to another embodiment of the present invention.
b is a table that provides a preferred set of bias conditions for various key 2-poly NVSRAM operations according to an embodiment of the present invention.
c is another timeline for operating the 2T Flash string of the 14T 2-poly NVSRAM cell according to another embodiment of the present invention.
The present invention is generally related with a novel design of static random-access memory (SRAM)-based non-volatile random-access memory (NVRAM) cell structure and array for an extremely fast write (program and erase) speed but low write and read voltage, for an extremely high-density, in-circuit or in-system programmable and erasable field-programmable gate array (FPGA) and NVRAM designs. More particularly, embodiments of the present invention provide a NVSRAM cell structure that is tailored for those SRAM-based FPGA IC designs with a stringent requirement of extremely high memory density of up to 1 Gb, a read operation with low-power Vdd down to 1.2V but with an extremely fast in-system repeatedly configurable speed of 10 ms.
More specifically, this invention is to provide a novel new SRAM-based NVRAM cell structure which is preferably comprised of one regular 6T SRAM CMOS cell and one pair of 4T Flash cell. Although the total number of transistors (T) of the present invention is 14, which may be larger than most of similar prior art, the NVAM cell structure and biased conditions and array operations have been much simplified to achieve the lower write voltage but faster write speed from the volatile SRAM cell into non-volatile Flash during the normal or unexpected power down mode or from non-volatile Flash data into volatile SRAM cell during normal Vdd power-up, collectively and simultaneously for whole extremely high-density FPGA array with density up to 1 Gb.
a is a schematic diagram of a 3T Flash string used in a NVSRAM cell of prior art. Presenting this traditional NVSRAM cell diagram is merely used as part of an inventive process as described below. As seen, a Flash string consists of two 1-poly HV NMOS Select transistors, ST1 and ST2, and one 2-poly floating-gate type NMOS Flash transistor, MC. The 1-poly Select transistor is formed by shorting Poly2 control-gate to Poly1 floating-gate. The three transistors of each Flash string are connected in series from the drain node of BL to the source node of SL. The channel widths of the three transistors are either made the same or different, depending on the applications and design specs.
There are well-known pros and cons for the 3T Flash string structure as summarized below.
1) Cons:
2) Pros:
b is a cross-sectional diagram of above 3T Flash string circuit used in a NVSRAM cell of prior art. Presenting this traditional NVSRAM cell diagram is merely used as part of an inventive process as described below. As seen, the two 1-poly HV NMOS Select transistors, ST1 and ST2, and one 2-poly floating-gate type NMOS transistor are all formed on the common P-sub. The top terminal of the Flash string is connected to BL (Metal bit line) and the bottom terminal is connected to SL (source line). The drawing has indicated ST1 and ST2 transistors' Poly2 and Poly1 gate being shorted to form a Poly1-gate NMOS device.
During the SBPI programming scheme, the channel of 2-poly flash transistor's voltage can be boosted up with HV value, ranging from 7V to 10V when flash gate voltage, FWL, is ramped to +18V. The electrical field between flash channel and Poly2 gate voltage, FWL, is then reduced to 11V. As a result, the electrical filed between the float-gate and channel is drastically reduced to below 3V providing the coupling ratio from flash control-gate to the floating-gate is around 70%. Thus the FN channel tunneling effect would not happen to the Program-Inhibited flash cell in one of the non-selected Flash string of each NVSRAM cell.
Conversely, the selected flash cell with its channel is held at Vss when its WL-gate is ramped to +18V during the program operation. The effective tunnel oxide electrical filed would exceed 10 mV/cm to induce the desired FN-channel tunneling effect. As a result, the selected flash cell's Vt would be increased above 2V in one of the selected Flash string of the selected NVSRAM cell after the Program operation.
c is a schematic diagram of a NVSRAM cell of prior art. It comprises a 6T CMOS SRAM cell on top and a Flash cell on bottom comprising of two 3T Flash strings as shown in
During each data writing from each 6T-SRAM cell into two Flash strings of each corresponding Flash cell, the word line of the SRAM cell (SWL) is grounded to isolate SRAM's latch from the global BL and BLB lines. That means the data writing is only performed exclusively between each 6T SRAM cell and each Flash cell in a local area.
The data writing from 1-bit 6T-SRAM into Flash is performed on two complementary flash bits (cells), MC1 and MC2, of two 3T Flash strings respectively denoted as FString 1 and FString2. In normal program operation, only one bit of MC1 and MC2 get programmed and one bit gets program-inhibited.
d is a table that provides a set of bias conditions for various key NVSRAM operations such as Erase and Program and Program-Inhibit of the Flash cell and Read of the SRAM cell of the NVSAM cell of prior art. Presenting these traditional NVSRAM operations is merely used as part of an inventive process as described below. Since this NVSRAM has 2-poly Flash string, thus the disadvantage of Erase and Program operating lies in the need to use much higher FWL voltages of −18V and +18V respectively.
The Vt level of the programmed flash cell would be Vt1 and is designed to be ≧+2V, while the Vt level of the inhibited flash cell would stay unchanged as the initial erased Vt level before program. The erased Vt level is Vt0 and is typically set to be ≦−2V. Therefore, in the beginning of Flash write operation, a FN-channel erase operation is performed prior to the FN-channel Program operation. After FN-channel Erase operation, both flash cells' Vts are erased to be identical with a targeted value ≦−2V. But after FN channel Program operation, one bit of the selected flash cell's Vt level would be increased to Vt1 of a value ≧2V. As a result, after FN program, the paired flash cells in the paired Flash strings would store two complementary Vts such as +2V of Vt1 and −2V of Vt0.
For example, if the SRAM's Q and QB data node are set to be Vdd and Vss, then the Vt level associated with the flash transistor MC1 would stay with Vt0 of −2V, while the Vt level associated with the flash transistor MC2 would be changed to Vt1 of +2V. As shown, the paired stored data of MC1 and MC2 are opposite of the stored data of paired Q and QB of each SRAM cell after FN channel Program. That would lead to wrongly loading Flash reverse data into each SRAM during the power up cycle if it is not handled correctly. Even worse is when the 1.2V Vdd operation is applied to the NVSRAM cell, correct loading of Flash data into SRAM cell will fail.
It is because the correct data loading from Flash cell to SRAM cell requires a high voltage value of Vdd−Vt(max) to set the SRAM cell into right state, where Vt(max) level is defined by the largest Vt value of transistors in each FString. Typically, the Vt levels of Select transistors ST1 and ST2 are the same with a value around 0.7V. But the Vt levels of the flash transistors MC1 and MC2 are set with complementary values of Vt1=+2V and Vt0=−2V. Therefore, the equivalent Vt(max) level of each FString is determined by the Select transistors ST's Vt level of 0.7V provided that the flash transistor MC's Vt level is at Vt0. By the contrast, the equivalent Vt(max) level of each FString is determined by the stored Vt1 of 2V associated with the flash transistor MC. When Vdd is 1.8V or higher, a current flow from FSL to charge either Q or QB node of the 6T-SRAM up to Vdd−Vt(max) to set the SRAM cell. If Q node is being charged up, then the Q voltage is set to be Vdd and QB is Vss. If the QB is being charged up, then QB voltage is Vdd but Q is Vss.
But when the operation of 1.2V Vdd operation is implemented for the NVSRAM, Vdd-Vt(max) becomes only 0.5V in the worst-case condition mentioned above, from which it is not high enough than Vt level of NMOS transistors of two invertors I1 and I2. As a result, the data loading from the Flash cell into the corresponding SRAM cell of each NVSRAM cell would fail at such the low 1.2V Vdd operation. Thus, using charge-up approach from FSL to Q or QB node of SRAM at the 1.2V Vdd operation is no longer valid. An improvement over the NMOS-type NVSRAM cell for 1.2V Vdd operation is needed.
a is another schematic diagram of a 3T Flash string used in another NVSRAM cell of prior art. Further, presenting this traditional NVSRAM cell diagram is merely used as part of an inventive process as described below. Similarly, the Flash string consists of two 1-poly HV NMOS Select transistors, ST1 and ST2, and one 1-poly but charge-trapping type, SONOS or MONOS, NMOS flash transistor, MC, unlike the Poly1-gate transistor of ST1 and ST2 shown in
b shows a cross-sectional diagram of above 3T 1-poly charge-trapping type Flash string circuit used in a NVSRAM cell of prior art shown in
c shows a similar schematic diagram of another NVSRAM cell of prior art. It also comprises a 6T CMOS SRAM cell on top and a Flash cell on bottom comprising of two 3T Flash strings as shown in
d shows a table that provides another set of bias conditions for various key operations of the NVSRAM cell of
However, when the 1.2V Vdd operation is implemented in the NVSRAM cell, the similar charge-up voltage of Vdd−Vt(max) becomes only 0.5V in the worst-case condition as mentioned above. The charge-up voltage Vdd−Vt(max) is not high enough to surpass the threshold voltage Vt level of NMOS transistor of the two invertors I1 and I2. As a result, the similar data loading from the two flash transistors, MC1 and MC2, into the corresponding data nodes of the SRAM cell of each NVSRAM cell would fail in such a low 1.2V Vdd operation. Thus, using the similar charge-up approach from a source line of the Flash cell (FSL) to either Q or QB data node of SRAM cell at 1.2V Vdd operation is no longer valid for this SONOS-type NVSRAM cell. An improvement for the SONOS-type NVSRAM cell in 1.2V Vdd operation is needed.
a is a schematic diagram of a 16T 2-poly NVSRAM cell according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. As shown, unlike the previous 2-poly NVSRAM cell shown in
Each Bridge circuit comprises four LV NMOS devices such as M3 and M5 with their common gate tied to FSwrite and M4 and M6 with their gates tied to SFwrite separately. These four LV 1-poly NMOS devices can be made exactly the same oxide-thickness of SRAM's NMOS devices in Inverters of I1 and I2 with same length and but larger channel width to achieve less resistance for the desired LV 1.2V Vdd operation. The details of operation between the paired Flash strings and each corresponding SRAM cell will be explained in accordance with the preferred set of bias conditions shown in
The definitions of signal names shown in
a) BL: Bit line
c) Q and QB: The paired input and output nodes of each 6T SRAM cell
d) SWL: SRAM's word line
e) SFwrite: Bridge connection control for writing each SRAM data directly into each Flash's string with the reversed data
f) FSwrite: The reversed Bridge connection control for writing each Flash period data into each SRAM's Q and QB with a correct data polarity
g) SG1: Top Select transistor gate's control signal of a 3T 2-poly FString
h) SG2: Bottom Select transistor gate's control signal of a 3T 2-poly FString
i) FWL: 2-poly Flash cell's gate word line control
j) FSL: 2-poly Flash string's source line.
There are several major differences of the preferred bias conditions shown in the table of
A second difference is that a two-routes connection is provided for each top paired nodes of each paired flash strings to the paired Q and QB nodes of each SRAM cell through two opposite Bridge connections between the SRAM cell and the Flash cell. As shown in
Further, only one of SFwrite and FSwrite is turned on at a time for two independent NVSRAM operations. In other words, the logic of SFwrite and FSwrite control lines is complementary during the data writing between the SRAM cell and Flash cell. But during normal SRAM operation, the Bridge circuit is disabled to make Flash cell in high impedance state compared to SRAM cell.
Furthermore, It is known that in the prior art for two NVSRAM writing operations, the Flash string source line FSL uses Vdd voltage to allow a current flow from the Flash string that stores Vt0 to charge the Q or QB node of the SRAM cell to set the SRAM cell data. Here in the present invention, instead of charging up Q or QB node, FSL is preferably held at Vss level upon the power-up cycle, the Q or QB node will be discharged to the Vss level through the Flash string that stores Vt0 to set data to the Q or QB node of the SRAM cell. Q or QB is associated with a “1” state if it is set to Vdd, otherwise is associated with a “0” state if it is set to Vss. This is especially applicable for 1.2V Vdd operation.
Referring to
Secondly, a Flash Program-Inhibit operation of the 2-poly NVSRAM cell also is executed using FN-channel scheme. The Program biased conditions and the preferable targeted specs are summarized as: a) Flash gate voltage, FWL ≦+12V; b) Flash drain voltage=Flash source voltage ≧5V with Psub=0V; c) Flash cell's Vt level stays with Vt0 without change after the Program operation.
Next, a SRAM normal Read operation is illustrated. In an embodiment, the Flash cell has to be isolated from the SRAM cell by grounding the top select gate, SG1. Other Flash control signals are in “X” state, where “X” means “don't-care.” In the embodiment, SWL has to be turned on by setting to Vdd when the SRAM cell is selected.
Additionally, a Writing Flash from SRAM operation is described below. In this operation, one paired flash cells in the paired Flash strings and one SRAM cell are involved. In a specific embodiment, only one HV signal of +12V is applied to the flash word line FWL. Bridge connection control signal SFwrite is held at Vdd to turn on Bridge transistors MC4 and MC6 to allow SRAM cell's paired Q and QB nodes to have a direct route connection to the paired flash cells MC1 and MC2 in the paired Flash strings (FString1 and FString2). Reversed Bridge connection control signal FSwrite is coupled to the ground Vss level to prevent the reversed route connection between the paired QB and Q nodes of SRAM cell to the paired flash cells MC1 and MC2. Within the one paired flash bits, only one flash bit is programmed to Vt1 level from initial erased value of Vt0 and the other complementary flash bit get program inhibited to keep it at the erased Vt0 value (≦−2V). The flash cell in the Flash string with Vdd applied to the drain terminal gets program inhibited, while the flash cell in the Flash string with Vss applied to the drain terminal get the programmed. After the Program operation, the Flash cell stored data (in the paired flash bits) is just opposite to Q and QB. For instance, if Q is “1” at Vdd level, then MC1 gets program inhibited to keep its Vt0 value unchanged, which is associated with a “0” state. On the contrary, QB is “0” at Vss level, then MC2 gets programmed and its Vt level becomes Vt1 level, which is associated with a “1” state.
The reason that MC1 gets program inhibited is because the Program scheme uses the Self-Boosting Program-Inhibit (SBPI) method. When the FWL control signal is ramped to +12V, channel bias level of the flash transistor MC1 would be coupled to above 5V, which will reduce the effective electrical field between its gate and the channel. As a result, FN-tunneling effect is not induced in this floating-gate flash transistor. Thus the Vt level of the flash transistor MC1 is not altered and stays with its initial Vt value, which is Vt0 (≦−2V) of an erased state. Conversely, when FWL control signal is ramped to +12V, channel bias level of the flash transistor MC2 is directly connected to the ground level Vss as both its drain and source are coupled to the Vss. As a high-coupling ratio of MC2 cell, the FN tunneling effect will be induced in the tunneling oxide of floating-gate flash transistor MC2. As a result, the Vt level od the flash transistor MC2 will be increased from initial Vt0 level to Vt1 (≧+2V). Therefore, a conclusion is: The Program operation of a NVSRAM cell of the present invention just needs one HV signal of +12V applied to the FWL control line which is much lower than a value of +18V or higher in prior art. The rest control signals are either set to Vdd or Vss. Thus, it is much easier to be executed for the NVSRAM cell operated at 1.2V Vdd power supply because smaller on-chip charge pump can be used to generate the required a reduced HV signal of +12V within 5 ms for an In-system programmable NVSRAM cell.
Further, a Writing SRAM from Flash operation is described. In this operation, one paired flash cells, MC1 and MC2, in the paired Flash strings and one SRAM cell are involved. In a specific embodiment, No HV signal is required and FWL is coupled to Vdd with FSL is Vss. Reversed Bridge connection control signal FSwrite is held at Vdd to turn on both Bridge transistors M3 and M5 for enacting the reversed route connection between the SRAM cell's paired QB and Q nodes to the paired flash cells MC1 and MC2 in the paired Flash strings. At the same time, Bridge connection control signal SFwrite is coupled to the ground level to prevent the direct route connection between the paired Q and QB nodes of SRAM cell to the paired flash cells MC1 and MC2. Within the paired flash bits MC1 and MC2, only one flash bit stored with the Vt0 level will conduct a current from Q or QB node to the FSL which is held at the Vss level. While the complementary flash bit stored with the Vt1 level will not conduct a current when the FWL is coupled to at Vdd. For instance, if the flash transistor MC1 stores a Vt0 level and correspondingly QB stores Vdd, the current will flow from QB node through the Bridge transistor M5, top Select transistor ST1, flash transistor MC1 and bottom Select transistor ST2, all gated to Vdd level, to the FSL held at the Vss level. In an embodiment, the ratio of I1 Inverter's PMOS resistance has to be lower than the total pull-down resistance of M5, ST1, MC1 and ST2. As a result, the QB node will be reset to Vss level to have same polarity of stored data of the flash transistor MC1.
In the prior art, since there is no Bridge circuit between the SRAM cell and the Flash cell to provide a reverse route connection, in order to set QB node to Vss, it has to set Q node to Vdd first. Further, in order to set Q node to Vdd, the FSL control signal has to be set to Vdd. Then the current flow (upward) is from FSL to Q node through the bottom Select transistor ST2, the flash transistor MC1 and the top Select transistor ST1 as shown in
Therefore, the conclusion about the Write from SRAM to Flash operation is that in order to write the same polarity data from each Flash cell into each SRAM cell of each NVSRAM at 1.2V Vdd operation, a preferred charge pull-down instead of a charge pull-up on Q or QB nodes of SRAM cell is justified of this invention for the NVSRAM cell operated at 1.2V Vdd.
Furthermore, a SRAM normal Read and Write operation is described. In a specific embodiment, each SRAM normal operation has to be not affected by each Flash part of each NVSRAM cell, regardless of Read and Write operation. In order to achieve that, both SFwrite and FSwrite control signals have to be grounded to completely isolate each Flash cell from each SARM cell. The rest of control signals of SG1, FWL, SG2 and FSL can be held at Vss. In order to make this 2-poly NVSRAM's SRAM fully compatible with traditional SRAM, the junction of Q- and QB-connected Flash path has to be made with a capacitance as small as possible. Since the SRAM cell has two PMOS devices that are formed within N-well, the silicon area is much bigger than the rest of NMOS transistors of two Invertors I1 and I2, the Bridge circuit, and two Flash strings, FString1 and FString2. As a result, the total area of overhead of the NVSRAM cell of the present invention is not high.
Referring to
c shows the preferred timelines for each operation of the 16T 2-poly NVSRAM cell of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. Although the timeline shows t1, t2, t3, t4 and t5 in X-axis, it is not intended to show a timing sequence. It just shows each operation with a preferred bias condition for the related control signals of the SRAM cell, the Bridge circuit, and a paired 3T Flash strings of
In a period of t1 to t2, it shows a bias conditions for all the control lines during a Flash Erase state. The SRAM cell is isolated from the Flash cell with both SFwrite and FSwrite control lines being set to Vss to shut down the connection. The top Select transistor gate line SG1 s grounded to isolate the HV signal from the flash transistor from affecting the SRAM cell. The bottom Select transistor gate line SG2 is set to Vdd to turn on that transistors of ST2 and ST4 to allow Vss connected to the source nodes of MC1 and MC2 flash cells for simultaneous erase operation in accordance with the bias conditions shown in
In a period of t2 to t3, it demonstrates a Flash Program/Program-Inhibit State during which the SRAM cell data, Q at Vdd and QB at Vss, is written into one of the flash transistor of the two 3T Flash strings. This state usually is triggered by a power-off moment. Correspondingly, SFwrite line is set to Vdd to open a direct route from the paired nodes of Q and QB to the paired Flash strings. SG1 is set to Vdd to open the gates of two top Select transistors ST1 and ST3 and SG2 is set to Vss to close the gates of two bottom Select transistors ST2 and ST4 for preventing charge leak to the flash source line FSL. Flash word line FWL is applied Vpp=+12V to induce FN tunneling effect in one string with QB drain node at Vss to write SRAM cell data to the flash cell, MC1, in corresponding Flash string while not inducing a FN tunneling in the other Flash string with Q drain node at Vdd to cause the corresponding flash cell, MC2, to be program-inhibited.
In another period of t3 to t4, a Flash Load into SRAM state is shown. This state is usually triggered by a power-up moment. SFwrite and FSwrite control lines are switched their setting at Vss and Vdd level to open a reverse route connection between the paired Flash bits and the paired nodes of QB and Q of the SRAM cell. All SG1, SG2, and FWL lines are set to Vdd, but only to allow a current flow only one Flash string with one flash bit stored with the Vt0 level from the Q or QB node to the FSL which is held at the Vss level. While the complementary flash bit stored with the Vt1 level will not conduct a current. The reversed route ensure the polarity of original SRAM data is correctly written back to correspond Q and QB node of the SRAM cell.
In yet another period of t4 to t5 showing bias conditions for a SRAM Read state. During the period, SRAM word line SWL is applied to Vdd to open the latch of SRAM and both SFwrite and FSwrite control signals are all coupled to ground level for isolating the SRAM cell from the Flash cell. All other control lines of the Flash cell is grounded.
a shows the second embodiment of the present invention of a 14T 2-poly NVSRAM cell according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. As shown,
b show a table that contains one set of detailed bias conditions of above said key operations of
Again, each NVSRAM operation is designed to be totally independent from the other operation. Only FWL control signal has four voltages levels such as Vpp, Vdd, Vss and Vnn. The rest of signals have only two voltages levels of Vdd and Vss. Since only FWL control signal requires Vpp of about +12V during the FN channel program operation, the charge time is quick because no P/N junction is involved. Thus an easier circuit control and smaller HV charge pump can be built in an on-chip configuration for a fast program operation within 10 ms for NVSRAM cell density as high as 200M bits.
c shows the preferred timelines for each operation of the 14T 2-poly NVSRAM cell according to an alternative embodiment of the present invention. As described before, this 14T 2-poly NVSRAM cell has only one paired bottom Select transistors sharing a common gate control line SG perpendicular to the two Flash strings. The timeline has removed gate control line SG1 and replaces SG2 by SG as explained above. Although the time shows t1, t2, t3, t4 and t5 in X-axis, it is not intended to show the timing sequence. It just shows each operation with a preferred bias condition for the related control signals of the SRAM cell, the Bridge circuit, and a paired 2T Flash strings of
In a specific embodiment, the present invention provides a 16T NVSRAM memory cell circuit with low-voltage fast-write scheme. The 16T NVSRAM memory cell includes a SRAM cell, a Flash cell, and a Bridge circuit coupling between the SRAM cell and the Flash cell. The SRAM cell is substantially illustrated in the top portion of the
The Flash cell is substantially illustrated in the bottom portion of the
The Bridge circuit is substantially illustrated in the middle portion of the
In a specific embodiment, only one of the FSwrite control line and the SFwrite control line is turned on at a time by coupling to a power supply voltage as low as 1.2 V Vdd. This operation scheme provides a direct route of writing data from the SRAM cell to the Flash cell via a FN tunneling effect by setting only one HV of +12V or lower to the second word line and provides an alternate route of loading data from the Flash cell to the SRAM cell by conducting current from the first or second data node to a grounded flash source line. The same operation scheme ensures a reversed polarity of each data from the Flash cell can be reversely loaded into the SRAM cell operating at the power supply voltage as low as 1.2 V Vdd.
In an alternative embodiment, the present invention provides a 14T NVSRAM memory cell circuit with low-voltage fast-write scheme. The 14T NVSRAM memory cell includes a SRAM cell, a Flash cell, and a Bridge circuit coupling between the SRAM cell and the Flash cell. In particular, the SRAM cell is a circuit depicted at the top portion of
The Flash cell is substantially depicted in the bottom portion of
The Bridge circuit is substantially one depicted in the middle portion of
In a specific embodiment, only one of the FSwrite control line and the SFwrite control line is turned on at a time by coupling to a power supply voltage as low as 1.2 V Vdd. This operation scheme provides a direct route of writing data from the SRAM cell to the Flash cell via a FN tunneling effect by setting only a HV of +12V to the second word line when the Flash transistor uses 2-poly floating-gate type NMOS transistor or an even lower voltage of +7V to the second word line when the Flash transistor uses 1-poly charge-trapping type SONOS or MONOS transistor. Further, this operation scheme provides an alternate route of loading data from the Flash cell to the SRAM cell by conducting current from the first or second data node to a grounded flash source line. The same operation scheme ensures a reversed polarity of each data from the Flash cell can be reversely loaded into the SRAM cell operating at the power supply voltage as low as 1.2 V Vdd.
Although the above has been illustrated according to specific embodiments, there can be other modifications, alternatives, and variations. It is understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
This application claims priority to U.S. Provisional Patent Application No. 61/688,107, filed on May 7, 2012, commonly assigned, and hereby incorporated by reference in its entirety herein for all purposes. This application is related to U.S. Pat. Nos. 8,018,768, 7,760,540, 7,110,293, and 7,859,899.
| Number | Date | Country | |
|---|---|---|---|
| 61688107 | May 2012 | US |
