Patent Application
20250203877
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2023-0185090 filed on Dec. 18, 2023, and 10-2024-0091822 filed on Jul. 11, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.
The disclosure relates to magnetic memory devices including tunneling magnetoresistance layers and memory devices including the magnetic memory devices.
A magnetic memory device such as magnetic random-access memory (MRAM) stores data by using a change in the resistance of a magnetic tunneling junction device. The resistance of the magnetic tunneling junction device varies with the relative magnetization direction of a free layer. For example, when the magnetization direction of the free layer is the same as the magnetization direction of a pinned layer, the magnetic tunneling junction device may have a lower resistance, and when the magnetization directions are opposite to each other, the magnetic tunneling junction device may have a higher resistance. When this characteristic is used in a memory device, for example, a magnetic tunneling junction device having a lower resistance may correspond to data ‘0’ and a magnetic tunneling junction device having a higher resistance may correspond to data ‘1’.
Such a magnetic memory device has advantages such as non-volatility, higher-speed operation, and/or higher durability. For example, spin transfer torque-magnetic RAM (STT-MRAM) that is currently mass-produced may have an operating speed of about 50 nanoseconds (nsec) to 100 nsec and also may have excellent data retention, e.g., of 10 years or more. In addition, spin orbit torque (SOT)-MRAM may have a very high operation speed less than or equal to 5 nsec, which is faster than the STT-MRAM because a spin polarization direction is perpendicular to the magnetization direction. Moreover, the SOT-MRAM may have more stable characteristics because a path of a write current and a path of a read current are different from each other.
Provided are a magnetic memory device including a tunneling magnetoresistance layer and a memory device including the magnetic memory device.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to an aspect of at least one embodiment, a magnetic memory device including a tunneling magnetoresistance layer including a free layer, a tunneling barrier layer, and a pinned layer, and a spin orbit torque (SOT) layer configured to provide a spin current, the spin current configured to change a magnetization direction of the free layer of the tunneling magnetoresistance layer, wherein the SOT layer includes an orbital Hall conductance (OHC) material layer configured to provide an orbital Hall current, and a conversion layer configured to convert the orbital Hall current into the spin current, and the OHC material layer includes at least one material of iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), or rhenium (Re).
The OHC material layer may include at least one of IrMn or PtMn.
The conversion layer may include at least one of platinum (Pt), terbium (Tb), gadolinium (Gd), samarium (Sm), or dysprosium (Dy).
The conversion layer may be between the OHC material layer and the tunneling magnetoresistance layer, and the free layer of the tunneling magnetoresistance layer may be between the conversion layer and the tunneling barrier layer.
The SOT layer may further include an in-plane magnetic anisotropy layer between the OHC material layer and the conversion layer, the free layer and the pinned layer may each have perpendicular magnetic anisotropy (PMA), and the in-plane magnetic anisotropy layer may have in-plane magnetic anisotropy.
The in-plane magnetic anisotropy layer may include at least one of cobalt (Co), iron (Fe), nickel (Ni), CoFe, FeB, CoFeB, or CoB.
The SOT layer may further include an insertion layer between the conversion layer and the tunneling magnetoresistance layer, and the insertion layer may include at least one of tungsten (W), tantalum (Ta), molybdenum (Mo), rhenium (Re), iridium (Ir), or ruthenium (Ru).
The SOT layer may further include a spin Hall conductance (SHC) material layer configured to generate the spin current due to a spin Hall effect, the SHC material layer may be provided between the OHC material layer and the conversion layer, the OHC material layer may include chromium (Cr), and the SHC material layer may include at least one of tungsten (W) or tungsten (βW) with a beta (β) phase.
The SOT layer may further include a SHC material layer configured to generate the spin current due to a spin Hall effect, the conversion layer is between the SHC material layer and the OHC material layer, the OHC material layer may include chromium (Cr), and the SHC material layer may include at least one of tungsten (W) or tungsten (βW) with a beta (B) phase.
The SOT layer may further include a seed layer configured to promote the beta (B) phase in the SHC material layer.
The seed layer may include at least one material of TaN, MgO, or CoFeB.
The free layer may include a first free layer, a second free layer, and an antiferromagnetic coupling layer between the first free layer and the second free layer, and a magnetization direction of the first free layer may be opposite to a magnetization direction of the second free layer.
The antiferromagnetic coupling layer may include at least one of ruthenium (Ru), iridium (Ir), tantalum (Ta), tungsten (W), palladium (Pd), zirconium (Zr), platinum (Pt), or aluminum (Al).
The magnetic memory device may further include a first electrode and a second electrode spaced apart from each other, the first electrode and second electrode configured to provide a write current between the first electrode and second electrode and through the SOT layer, and a third electrode electrically connected to the pinned layer such that the third electrode and at least one of the first electrode or the second electrode are configured to provide a read current through the tunneling magnetoresistance layer and the SOT layer.
According to an aspect of at least one embodiment, a memory device including a plurality of memory cells each including a magnetic memory device and a switching device connected to the magnetic memory device, wherein the magnetic memory devices includes a tunneling magnetoresistance layer including a free layer, a tunneling barrier layer, and a pinned layer, and a spin orbit torque (SOT) layer configured to provide a spin current, the spin current configured to change a magnetization direction of the free layer of the tunneling magnetoresistance layer, wherein the SOT layer includes an OHC material layer configured to provide an orbital Hall current, and a conversion layer configured to convert the orbital Hall current of the OHC material layer into the spin current, and the OHC material layer includes at least one of iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), or rhenium (Re).
The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
Hereinafter, with reference to the accompanying drawings, a magnetic memory device including a tunneling magnetoresistance layer and a memory device including the magnetic memory device will be described in detail. Like reference numerals refer to like elements throughout, and in the drawings, sizes of elements may be exaggerated for clarity and convenience of explanation. The embodiments described below are merely examples, and various modifications may be possible from the embodiments.
In a layer structure described below, an expression “on/below” may include not only “immediately on/below in a contact manner” but also “on/below in a non-contact manner”. It will also be understood that spatially relative terms, such as “above”, “top”, etc., are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures, and that the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein interpreted accordingly. An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context. It will be further understood that the terms “comprises” and/or “comprising” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.
The use of “the” and other demonstratives similar thereto may correspond to both a singular form and a plural form. Unless the order of operations of a method according to the disclosure is explicitly mentioned or described otherwise, the operations may be performed in a proper order. The disclosure is not limited to the order the operations are mentioned.
The functional elements, including those indicated by terms such as “unit” or “module”, indicates a unit for processing at least one function or operation, and may be implemented in processing circuitry, such as hardware or software, or in a combination of hardware and software. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc., and/or electronic circuits including said components.
The connecting lines, or connectors shown in the various figures presented are intended to represent functional relationships and/or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may be present in a practical device.
The use of any and all examples, or language provided herein, is intended merely to better illuminate the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. Additionally, when the terms “about” or “substantially” are used in this specification in connection with a numerical value and/or geometric terms, it is intended that the associated numerical value includes a manufacturing tolerance (e.g., ±10%) around the stated numerical value. Further, regardless of whether numerical values and/or geometric terms are modified as “about” or “substantially,” it will be understood that these values should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values and/or geometric. When referring to “C to D”, this means C inclusive to D inclusive unless otherwise specified.
The tunneling magnetoresistance layer 120 may include a free layer 121 provided on the SOT layer 110, a tunneling barrier layer 122 provided on the free layer 121, and a pinned layer 123 provided on the tunneling barrier layer 122. The expression “provided on” is for convenience of explanation and does not necessarily mean a top-down relationship. To put it another way, the free layer 121 and the pinned layer 123 may face each other, and the tunneling barrier layer 122 may be provided between the free layer 121 and the pinned layer 123. Also, the tunneling magnetoresistance layer 120 may be provided such that the free layer 121 is in direct contact with the SOT layer 110 and/or such that the free layer 121 is provided between the tunneling barrier layer 122 and the SOT layer 110.
The free layer 121 and the pinned layer 123 may each include a ferromagnetic metal material having magnetism. For example, the free layer 121 and the pinned layer 123 may each include a ferromagnetic material including at least one of iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), a Fe-containing alloy, a Co-containing alloy, a Ni-containing alloy, a Mn-containing alloy, and/or a Heusler alloy (or “Heusler compound”). The free layer 121 and the pinned layer 123 may each include the same ferromagnetic material, but are not limited thereto. In addition, the free layer 121 may further include boron (B) to improve wetting characteristics of the free layer 121 in a process of depositing the free layer 121. For example, the free layer 121 may include CoFeB.
In addition, the free layer 121 and the pinned layer 123 may each be configured to have high perpendicular magnetic anisotropy (PMA). In other words, PMA energy of each of the free layer 121 and the pinned layer 123 may exceed out-of-plane magnetization energy. In this case, a magnetic moment of each of the free layer 121 and the pinned layer 123 may be stabilized in a thickness direction (e.g., a Z direction) or in a direction perpendicular to a plane direction (e.g., an X direction).
The pinned layer 123 may have a pinned magnetization direction. Once determined, the magnetization direction of the pinned layer 123 may not be changed during the operation and/or lifetime of the magnetic memory device 100. On the other hand, the free layer 121 may have a variable magnetization direction. The tunneling magnetoresistance layer 120 may have a relatively low resistance when the magnetization directions of the free layer 121 and the pinned layer 123 are the same (e.g., parallel), and may have a relatively high resistance when the magnetization directions of the free layer 121 and the pinned layer 123 are opposite (e.g., anti-parallel). This phenomenon is called tunneling magnetoresistance (TMR).
The free layer 121 may have a relatively low saturation magnetization (Ms) such that the magnetization direction may be easily changed (e.g., switched). To this end, the free layer 121 may be doped with at least one non-magnetic metal as a dopant. The dopant may include, for example, at least one of magnesium (Mg), ruthenium (Ru), iridium (Ir), titanium (Ti), zinc (Zn), gallium (Ga), tantalum (Ta), aluminum (Al), molybdenum (Mo), zirconium (Zr), tin (Sn), tungsten (W), antimony (Sb), vanadium (V), niobium (Nb), chromium (Cr), germanium (Ge), silicon (Si), hafnium (Hf), terbium (Tb), scandium (Sc), yttrium (Y), rhodium (Rh), indium (In), calcium (Ca), strontium (Sr), barium (Ba), beryllium (Be), vanadium (V), lithium (Li), cadmium (Cd), palladium (Pb), and/or gallium (Ga). A doping concentration of the non-magnetic metal in the free layer 121 may be in a range of, for example, about 5 at % to about 50 at %.
The tunneling barrier layer 122 may serve as a tunnel barrier for a magnetic tunneling junction. The tunneling barrier layer 122 may include crystalline magnesium (Mg) oxide. For example, the tunneling barrier layer 122 may include at least one of MgO, MgAl2O4, and/or MgTiOx (wherein x represents an integer).
The free layer 121 is configured such that the magnetization direction of the free layer 121 may be changed by a SOT generated due to a spin current generated in the spin orbit torque layer 110. In this regard, the magnetic memory device 100 may be applied to a SOT magnetic random-access memory (MRAM). The SOT layer 110 may switch the magnetization direction of the free layer 121 by providing the spin current to the tunneling magnetoresistance layer 120, especially the free layer 121, according to the current flowing through the SOT layer 110. For example, the free layer 121 may be magnetized in a +Z direction or a −Z direction according to a direction of the current applied to the SOT layer 110.
According to at least one embodiment, the SOT layer 110 may be configured to lower an operating current density for switching the magnetization direction of the free layer 121. To this end, the SOT layer 110 may generate a relatively large spin current even with a relatively low operating current density. The amount of spin current generated in the SOT layer 110 may increase as a spin Hall angle (SHA), which is the efficiency at which a charge current is converted into the spin current by the spin Hall effect, increases, and a spin Hall conductance (SHC) of the SOT layer 110 itself by the spin Hall effect increases.
Among the currently known materials, platinum (Pt) is a material with high SHA and SHC, but platinum (Pt) alone has limitations in increasing the SHC. According to at least one embodiment, the amount of spin current generated in the SOT layer 110 may be increased by using a material with an orbital Hall conductance (OHC) greater than the SHC of platinum (Pt) and a material converting an OHC of the material into the SHC together, based on the fact that there is a material whose OHC obtained by an orbital Hall effect is greater than the SHC of platinum (Pt).
For example, the SOT layer 110 may include an OHC material layer 111 that provides an orbital Hall current and a conversion layer 112 that converts the orbital Hall current into the spin current. The conversion layer 112 may be provided on the OHC material layer 111, and the tunneling magnetoresistance layer 120 may be provided on the conversion layer 112. In other words, the conversion layer 112 may be provided between the OHC material layer 111 and the tunneling magnetoresistance layer 120, particularly between the OHC material layer 111 and the free layer 121. In at least one embodiment, the free layer 121 of the tunneling magnetoresistance layer 120 is provided to be in direct contact with the conversion layer 112.
The OHC material layer 111 may include an element having a relatively large OHC and/or an alloy thereof. For example, the OHC material layer 111 may include at least one of iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), tungsten (W), rhenium (Re), and/or an alloy thereof. For example, the alloy may include IrMn and/or PtMn. A thickness of the OHC material layer 111 may be, for example, about 1 nanometers (nm) or more and/or about 10 nm or less. For example, the thickness of the OHC material layer 111 may be within a range of about 3 nm to about, and/or about 4 nm to about 6 nm.
The conversion layer 112 may include, for example, platinum (Pt) and/or at least one rare earth element among terbium (Tb), gadolinium (Gd), samarium (Sm), and/or dysprosium (Dy). A thickness of the conversion layer 112 may be about 0.1 nm or more and/or about 5 nm or less. For example, thickness of the conversion layer 112 may be within of a range of about 0.5 nm to about 4 nm, and/or about 1 nm to about 3 nm.
According to at least one embodiment, the orbital Hall current may be generated in the OHC material layer 111 when a current is applied to the OHC material layer 111 including a material having a relatively large OHC. The orbital Hall current may be converted into the spin current by the conversion layer 112. In addition, because the current also flows in the conversion layer 112, a spin current may also be generated by the spin Hall effect in the conversion layer 112 itself. Therefore, the SOT layer 110 according to at least one embodiment may generate a large spin current compared to a case in which platinum (Pt) is used alone. Then, even if the current applied to the SOT layer 110 is relatively small, a spin current sufficient to perform magnetic switching on the free layer 121 of the tunneling magnetoresistance layer 120 may be obtained, and the operating current density of the magnetic memory device 100 may be reduced.
The magnetic memory device 100 may further include a first electrode 131 and a second electrode 132 for applying a current to the SOT layer 110. The first electrode 131 and the second electrode 132 may be spaced apart from each other on a lower surface of the SOT layer 110, particularly on a lower surface of the OHC material layer 111. When a voltage is applied to each of the first electrode 131 and the second electrode 132, the orbital Hall current may be generated while a current flows in the OHC material layer 111. Also, the magnetic memory device 100 may include a third electrode 133 for reading the resistance of the tunneling magnetoresistance layer 120. The third electrode 133 may be electrically connected to the pinned layer 123. Thereby, a current may be supplied between the first electrode 131 and the second electrode 132 during a write operation, and between the third electrode 133 and at least one of the first electrode 131 and the second electrode 132 during a read operation, as discussed in further detail below.
Referring to
As described above, because the magnetic memory devices 100 and 100a according to the example embodiments perform magnetic switching on the free layer 121 by using the SOT, the magnetic memory devices 100 and 100a may each have a higher operation speed than a magnetic memory device using only a spin-transfer torque (STT). For example, the magnetic memory devices 100 and 100a according to the example embodiments may have a relatively high operation speed of about 5 nsec or less and/or about 1 nsec or less. In addition, because the magnetic memory devices 100 and 100a according to the example embodiments may operate at a relatively low current density while having the high operation speed, the magnetic memory devices 100 and 100a may each have a relatively low power consumption.
The free layer 121′ may have a structure of a synthetic antiferromagnet. For example, the free layer 121′ may include a first free layer 121a, an antiferromagnetic coupling layer 124 provided on the first free layer 121a, and a second free layer 121b provided on the antiferromagnetic coupling layer 124. In other words, the first free layer 121a and the second free layer 121b may face each other, and the antiferromagnetic coupling layer 124 may be provided between the first free layer 121a and the second free layer 121b. The first free layer 121a may be provided adjacent to the SOT layer 110, and the second free layer 121b may be provided adjacent to the tunneling barrier layer 122.
The first free layer 121a and the second free layer 121b may each include the ferromagnetic metal material described above. For example, the first free layer 121a and the second free layer 121b may each include at least one ferromagnetic material including iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), a Fe-containing alloy, a Co-containing alloy, a Ni-containing alloy, a Mn-containing alloy, and/or a Heusler alloy. The first free layer 121a and the second free layer 121b may each include the same ferromagnetic material, but are not limited thereto. In addition, at least one of the first free layer 121a and the second free layer 121b may further include boron (B) to improve wetting characteristics. In addition, at least one of the first free layer 121a and the second free layer 121b may be doped with at least one non-magnetic metal. The dopant may include, for example at least one of Mg, Ru, Ir, Ti, Zn, Ga, Ta, Al, Mo, Zr, Sn, W, Sb, V, Nb, Cr, Ge, Si, Hf, Tb, Sc, Y, Rh, In, Ca, Sr, Ba, Be, V, Li, Cd, Pb, and/or Ga and may be selected based the ferromagnetic material to reduce the saturation magnetization of the corresponding first free layer 121a and the second free layer 121b. For example, the first free layer 121a may include cobalt (Co) and/or CoNi, and the second free layer 121b may include CoFeB.
The antiferromagnetic coupling layer 124 may include a non-magnetic metal that generates a Dzyaloshinskii-Moriya interaction at an interface with the first free layer 121a and at an interface with the second free layer 121b. For example, the antiferromagnetic coupling layer 124 may include at least one of ruthenium (Ru), iridium (Ir), tantalum (Ta), tungsten (W), palladium (Pd), zirconium (Zr), platinum (Pt), aluminum (Al), and/or an alloy thereof selected based on the Dzyaloshinskii-Moriya interaction with the first free layer 121a and the second free layer 121b.
In this structure, the first free layer 121a and the second free layer 121b may form an antiferromagnet through the antiferromagnetic coupling layer 124. In other words, the free layer 121′ may have a stable state when a magnetization direction of the first free layer 121a and a magnetization direction of the second free layer 121b are opposite to each other.
The magnetic memory device 100b having the above-described structure may also be applied to a racetrack memory. The racetrack memory is a memory in which a plurality of domain walls are arranged in a layer direction (e.g., the X direction) inside the free layer 121′ and data is recorded by using the movement of a magnetic wall. The racetrack memory may store multi-bit data by using a plurality of magnetic walls of the free layer 121′. To form the plurality of magnetic walls, the free layer 121′ may be formed relatively long in the layer direction (e.g., the X direction). Even in the racetrack memory, because the magnetic wall is moved by using the spin current generated by the SOT layer 110, when a SHC increases, an operating current may be reduced. Therefore, the operating current of the racetrack memory may be reduced through the relatively large spin current generated in the SOT layer 110 including the OHC material layer 111 and the conversion layer 112.
The in-plane magnetic anisotropy layer 113 may include a ferromagnetic metal material. For example, the in-plane magnetic anisotropy layer 113 may include a ferromagnetic metal material including at least one of cobalt (Co), iron (Fe), nickel (Ni), CoFe, FeB, CoFeB, and/or CoB. The in-plane magnetic anisotropy layer 113 may be configured such that a magnetization direction of the ferromagnetic material is fixed in a plane direction (e.g., the X direction or a horizontal direction). In this case, a spin current in a direction perpendicular to the plane direction or in the thickness direction (e.g., the Z direction) may be generated near an interface between the in-plane magnetic anisotropy layer 113 and the conversion layer 112. Then, when performing magnetic switching on the free layer 121, it is not necessary to apply a separate external magnetic field in the horizontal direction. In this regard, it may be seen that the in-plane magnetic anisotropy layer 113 serves as an external magnetic field. Thus, the magnetic memory device 100c may be configured to field-free switch without requiring the external magnetic field, e.g., when performing magnetic switching on the free layer 121 by using the in-plane magnetic anisotropy layer 113.
When the in-plane magnetic anisotropy layer 113 is present near the free layer 121 having perpendicular magnetic anisotropy (PMA), the PMA of the free layer 121 may be weakened. Therefore, the insertion layer 114 may serve to enhance the PMA of the free layer 121. To this end, the insertion layer 114 may include a metal material selected to enhance the PMA of the free layer 121. For example, the insertion layer 114 may include at least one of tungsten (W), tantalum (Ta), molybdenum (Mo), rhenium (Re), iridium (Ir), and ruthenium (Ru), and/or an alloy thereof selected based on the material of the free layer 121.
The SHC material layer 115 may include a metal material having a relatively large SHC. The relatively large SHC of the SHC material layer 115 may additionally generate a spin current due to the spin Hall effect. Therefore, the spin current generated in the SOT layer 110d may be further increased through a combination of the OHC material layer 111 and the SHC material layer 115. The SHC material layer 115 may include, for example, tungsten (W) and/or tungsten (BW) having a beta (B) phase. The OHC material layer 111 may include, for example, at least one of iridium (Ir), manganese (Mn), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), and rhenium (Re), and/or an alloy thereof. The OHC material layer 111 may include, for example, chromium (Cr).
In this structure, a write current IW or a read current IR may be applied to the memory cell MC through the word line WL, the source line SL, and the bit line BL. For example, when a voltage higher than a threshold voltage is applied to the word line WL and a current higher than a threshold current is applied to the source line SL, the switching device TR may be turned on, and the write current IW may flow through a path between the first electrode 131 and the second electrode 132 of the magnetic memory device 100. At this time, the second electrode 132 of the magnetic memory device 100 may be grounded. Then, a magnetization direction of the free layer 121 may be changed into the +Z direction or the −Z direction according to a direction of the current applied to the SOT layer 110.
Additionally, the read current IR may flow from the first electrode 131 of the magnetic memory device 100 to the bit line BL through the third electrode 133. For example, when the voltage higher than the threshold voltage is applied to the word line WL and a current lower than a threshold current is applied to the source line SL, the switching device TR may be turned on, and the read current IR may flow to the bit line BL through the first electrode 131 and the third electrode 133 of the magnetic memory device 100. At this time, the second electrode 132 of the magnetic memory device 100 may be in a floating state. Then, a resistance value of the magnetic memory device 100 may be read by measuring the current flowing through the bit line BL.
The above-described memory device 200 and/or the above-described magnetic memory devices 100 to 100g shown in
It should be understood that the example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0185090 | Dec 2023 | KR | national |
| 10-2024-0091822 | Jul 2024 | KR | national |
