Patent Application
20100207952
Embodiments of the invention relate display drivers and to systems that include display drivers.
The displays used in many human interface devices come in various formats such as computer display (VGA, SVGA etc.,), cell phones, PDA, Mini LCD displays, Digital cinema, Video conferencing format, Digital Television format and more. Existing forms of display memory buffers are implemented with memory technologies such as SRAM (Static Random Access Memory), 1-TSRAM (1-Transistor Static Random Access Memory). These memory technologies suffer from the disadvantages of huge static power consumption and require periodic memory refresh. The display driver chip with integrated buffer memory needs to fit certain physical form factors dictated by the display dimensions. As the demand for higher resolution increases over every display generation the buffer memory requirement also increases steadily. Moreover, it is becoming increasingly difficult to scale the SRAM and 1T-SRAM to fit the physical dimensions allowed.
In one embodiment, there is provided a display driver system that includes an MRAM storage aread.making MRAM for display driver applications that involves the integration of MRAM core and the current drivers to drive the display matrix in a single semiconductor device.
In one embodiment, the invention discloses the application of Magnetic Random Access Memory (MRAM) to implement display drivers. MRAMs may be implemented using Field Induced Switching, Spin Torque Transfer, Thermally Assisted Switching and others. The method comprises of implementing the buffer memory using MRAM in which the processor stores and retrieves data corresponding to the display pixel information.
In another embodiment, the invention discloses a MRAM memory device architecture that implements the buffer memory of the display driver. The memory device may comprise an array of bits, each to store data and having a memory address; a read circuit for reading data from selected bits in the array based on a memory address of the selected bits; and a write circuit for writing data to the array given write data and a memory address in the array at which to write the write data.
In another embodiment the invention discloses an MRAM memory device that implements MRAM memory and the drivers for driving the display.
Other aspects of the invention will be apparent from the detailed description below:
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details.
Reference in this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.
Magnetic random access memory (MRAM) devices are capable of storing data without consuming static power. Further, MRAM devices do not require data refresh and enjoy a smaller size footprint when compared to other memory device. Advantageously, embodiments of the present invention disclose a display driver system that incorporates MRAM technology. Embodiments of the present invention also disclose an electronic device that incorporates the display driver system.
Referring to
In accordance with one embodiment, the MRAM Macro comprises an array of randomly addressable MRAM cells with necessary addressing, writing and sensing circuitry, as will be understood by one of ordinary skill in the art. The MRAM cells may be written and read using induced magnetic field (Field Induced Magnetic Switching), Spin Torque Transfer, Thermally Assisted Switching or any other magnetic switching methods. The MRAM macro 20 communicates with the processor 26 through the I/O bus 24. The processor 26 stores data in and retrieves data from the MRAM macro 20.
Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that the various modification and changes can be made to these embodiments without departing from the broader spirit of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than in a restrictive sense.
This application claims the benefit of priority to U.S. Provisional Patent Application No. 61/152,928 filed Feb. 16, 2009.
| Number | Date | Country | |
|---|---|---|---|
| 61152928 | Feb 2009 | US |
