This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-144303, filed Sep. 3, 2021, the entire contents of which are incorporated herein by reference.
Embodiments of the present disclosure described herein relate generally to a magnetic memory.
A magnetic memory in which a magnetic wall of a magnetic member formed of a magnetic material is moved or shifted by a current (hereinafter referred to as a shift current) passing through the magnetic member is known. In such a magnetic memory, a magnetization direction is written to the magnetic member by a write current passing through a write wiring or a field line disposed close to the magnetic member. The written magnetization direction corresponds to stored bit information. Accordingly, the write energy consumption per bit may become large.
Embodiments provide a magnetic memory having a reduced a write current per bit.
In general, according to one embodiment, a magnetic memory includes an electrode extending along a plane including a first direction and a second direction intersecting the first direction, first and second wirings extending along the first direction, a first magnetic member including a first portion electrically coupled to the first wiring and a second portion electrically coupled to the electrode, the first magnetic member extending along a third direction intersecting the first and second directions, a second magnetic member including a third portion electrically coupled to the second wiring and a fourth portion electrically coupled to the electrode, the second magnetic member extending along the third direction, a third wiring extending along the second direction between the electrode and each of the second and fourth portions, and a control circuit electrically coupled to the first, second, and third wirings and the electrode. The control circuit is configured to supply a first current to the third wiring to generate a magnetic field and magnetize in a first magnetization direction a magnetic domain of each of the second and fourth portions, the magnetic domain storing information represented by magnetization directions thereof, and supply a second current between the electrode and each of the first and second wirings to respectively shift the magnetic domains of the second and fourth portions towards the first and third portions.
Hereinafter, certain example embodiments of the present disclosure will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the depicted dimensions (thickness and length/width) of each part or component, the ratio of the sizes of the parts and components, and the like are not always the same as the actual ones. Likewise, the dimensions of the same part may be represented differently depending on the drawing. In present disclosure, the same elements are designated using the same reference numerals, and the description of such elements may be omitted.
A magnetic memory according to a first embodiment will be described with reference to
As shown in
In
In the magnetic member 12ij (i, j=1 and 2), as shown in
d1>d2,d1>d4, and
d3>d2,d3>d4.
The distances d1, d2, d3, d4 taken in cross-section correspond to diameters (outer diameters) of the magnetic members 12ij.
In the magnetic member 12ij (i, j=1 and 2), at the first end portion 12a, a flange portion 12e extending along a surface intersecting in the z direction is provided, and at the second end portion 12b, a flange portion 12f extending along a surface intersecting in the z direction is provided. The flange portions 12e and 12f include the same vertical magnetic material as the magnetic member 12ij (i, j=1 and 2). The first end portion 12a of the magnetic member 12ij (i, j=1 and 2) is electrically coupled to the magnetoresistive element 14 via the flange portion 12e and a non-magnetic conductive layer 13 (see
The magnetoresistive element 14ij (i, j=1 and 2) reads out the information written in the magnetic member 12ij (i, j=1 and 2), and is made of, for example, a magnetic tunnel junction (MTJ) element. Hereinafter, the magnetoresistive element 14ij (i, j=1 and 2) will be described as an MTJ element. The MTJ element 14ij (i, j=1 and 2) includes a magnetization free layer 14a with a variable magnetization direction, a magnetization fixed layer 14c with a fixed magnetization direction, and a non-magnetic insulating layer 14b disposed between the free layer 14a and the fixed layer 14c. The non-magnetic insulating layer may be referred to as the tunnel barrier layer. In the MTJ element 14ij (i, j=1 and 2), the free layer 14a is electrically coupled to the first end portion 12a of a magnetic member 12 via the non-magnetic conductive layer 13, and the fixed layer 14c is electrically coupled to the bit wiring BL. Here, “the magnetization direction is variable” means that the magnetization direction can be changed by the leakage magnetic field from the magnetic member 12ij (i, j=1 and 2) in the read operation described later, and “the magnetization direction is fixed” means that the magnetization direction does not change due to the leakage magnetic field from the magnetic member 12ij (i, j=1 and 2).
The vertical thin film transistor 18ij (i, j=1 and 2) has one end electrically coupled to the fixed layer 14c of the magnetoresistive element 14ij via a non-magnetic conductive layer 15 and the other end electrically coupled to the bit wiring BLi via a non-magnetic conductive layer 19, and includes a channel layer 18a extending along the z direction and a gate electrode portion SGj that surrounds or sandwiches the channel layer 18a. That is, the gate electrode portion SGj covers at least a portion of the channel layer 18a. The channel layer 18a includes, for example, crystalline silicon. The gate electrode portion SGj extends along the y direction.
Further, the second end portion 12b of the magnetic member 12ij (i, j=1 and 2) is electrically coupled to the plate electrode PL via a non-magnetic conductor 30. That is, the plate electrode PL is shared by each memory unit 10ij (i, j=1 and 2). One end of the non-magnetic conductor 30 is positioned inside the second end portion 12b of the magnetic member 12ij.
The field line FLj (j=1 and 2) extends along the y direction and is disposed between the flange portion 12f of the second end portion 12b and the plate electrode PL. The field line FL1 is provided for the memory units 1011 and 1021, and the field line FL2 is provided for the memory units 1012 and 1022. A yoke 40 surrounds the field line FLj (j=1 and 2). The yoke 40 includes a first portion 40a, a second portion 40b, a third portion 40c, and a fourth portion 40d, and forms a magnetic circuit that strengthens the magnetic field generated when a current is passed through the field line FLj (j=1 and 2).
The first portion 40a of the yoke 40 covers a portion of the upper surface of the field line FLj (j=1 and 2) and the side surface opposite to the non-magnetic conductor 30. The second portion 40b is disposed below the field line FLj (j=1 and 2) and the flange portion 12f of the magnetic member 12ij (i, j=1 and 2), and surrounds the second end portion 12b of the magnetic member 12ij (i, j=1 and 2). The third portion 40c covers the upper surface of the flange portion 12f and one end of the non-magnetic conductor 30. That is, since the end of the non-magnetic conductor 30 positioned inside the second end portion 12b of the magnetic member 12ij, (j=1 and 2) is covered, this covering portion of the third portion 40c is disposed inside the second end portion 12b. The fourth portion 40d is coupled to the third portion 40c and covers the side surface of the field line FL on the side of the non-magnetic conductor 30 and a portion of the upper surface of the field line FLj (j=1 and 2).
The plate electrode PL, the bit wiring BLi (i=1 and 2), the gate electrode portion SGj, and the field line FLj (j=1 and 2) are electrically coupled to the control circuit 100. A constant voltage can be applied to the plate electrode PL.
In the first embodiment, it is preferable that the magnetic members 1211 to 1222 are disposed such that, as shown in
Next, data write and data read operations in the magnetic memory of the first embodiment will be described with reference to
Regarding the write method in the magnetic memory of the present embodiment, in the magnetic memory provided with the memory units 1011 to 1044 arranged in 4 rows and 4 columns, among the memory units 1011, 1021, 1031, and 1041 arranged in the y direction along which the field line FL1 extends, the information “1” is written in the memory units 1011 and 1031, and the information “0” is written in the memory units 1021 and 1041. Here, the information “1” indicates that the magnetization direction of the magnetic member 12ij (i=1 to 4, j=1 to 4) is one of an outward or inward direction in the radial direction, and the information “0” indicates the other one of the outward or inward directions.
First, as shown in
Next, as shown in
Subsequently, as shown in
Next, as shown in
As described above, in the present embodiment, a first write current is passed through the field line FL1, first information is collectively written to the memory units 10ij arranged along the field line FL1, and a shift current is selectively supplied to a first memory unit group to store the first information that has been written. Subsequently, a second write current in the direction opposite to that of the first write current is passed through the field line FL1 and second information different from the first information is collectively written to the memory units 10ij arranged along the field line FL1, the shift current is selectively supplied to a second memory unit group different from the first memory unit group, and the second information is stored. That is, since the write is performed such that the information is collectively written to the memory units 10ij arranged along the field line FL1, an increase in write energy consumption per bit can be prevented.
Next, the read operation will be described with reference to
When the information to be read are not present at the lowermost portion of the magnetic member 1211 of the memory unit 1011, a shift current is supplied between the bit wiring BL1 and the plate electrode PL by the control circuit 100, and the information to be read is moved to be positioned at the lowermost portion of the magnetic member 1211. After that, the information can be read by performing the read operation mentioned above.
As described above, according to the present embodiment, since the write is performed such that the information is collectively written to the memory units 10j arranged along the field line FL1, an increase in write energy consumption per bit can be prevented.
Further, according to the present embodiment, in the magnetic member 12j (i, j=1 and 2), since the first end portion 12a is electrically coupled to the magnetoresistive element 14ij and the second end portion 12b is electrically coupled to the plate electrode PL, it is possible to highly integrate the magnetic member 12ij. Further, in the present embodiment, the vertical thin film transistor 18ij is used as a selection element that selects the memory unit 10ij (i, j=1 and 2). Accordingly, as compared with a case where a two-terminal switching element is used as the selection element, the hold current required for the two-terminal switching element becomes unnecessary, and the margin between the read current value and the shift current value can be expanded.
The magnetic memory according to a second embodiment is shown in
The memory unit 10Aij (i, j=1 and 2) includes the magnetic member 12ij, the magnetoresistive element 14ij, the non-magnetic conductive layer 15, the vertical thin film transistor 18ij, the non-magnetic conductive layer 19, the bit wiring BLi, the yoke 50, the plate electrode PL, and the field line FLj.
The yoke 50 includes a first portion 50a and a second portion 50b. The first portion 50a has the same shape as the plate electrode PL shown in
In the magnetic member 12ij (i, j=1 and 2), the first end portion 12a is electrically coupled to the free layer 14a of the magnetoresistive element 14ij via the flange portion 12e. The fixed layer 14c of the magnetoresistive element 14ij (i, j=1 and 2) is electrically coupled to one end of the vertical thin film transistor 18ij via the non-magnetic conductive layer 15. The other end of the vertical thin film transistor 18ij (i, j=1 and 2) is electrically coupled to the bit wiring BLi via the non-magnetic conductive layer 19. The bit wiring BLi (i=1 and 2) extends along the x direction, the gate electrode portion SGj of the vertical thin film transistor 18ij (i, j=1 and 2) extends along the y direction, and the field line FLj extends along the y direction.
The write operation in the magnetic memory configured in this way is performed in the same manner as the magnetic memory of the first embodiment described with reference to
In the second embodiment also, as in the first embodiment, since the write is performed such that the information is collectively written to the memory units 10ij arranged along the field line FL1, an increase in write energy consumption per bit can be prevented.
Further, in the magnetic memory of the second embodiment, as in the first embodiment, since in the magnetic member 12ij (i, j=1 and 2), the first end portion 12a is electrically coupled to the magnetoresistive element 14 and the second end portion 12b is electrically coupled to the plate electrode PL, it is possible to highly integrate the magnetic member 12ij. Further, in the present embodiment, the vertical thin film transistor 18ij (i, j=1 and 2) is used as a selection element that selects the memory unit 10A. Accordingly, as compared with a case where a two-terminal switching element is used as the selection element, the hold current required for the switching element becomes unnecessary, and the margin between the read current value and the shift current value can be expanded.
The magnetic memory according to a modification example of the second embodiment will be described with reference to
Each magnetic member 1211 (j=1 to 4) has a first end portion 12aij, as in the case of the second embodiment shown in
The other end of the vertical thin film transistor 18ij (j=1 to 4) is electrically coupled to the bit wiring BL1 via the non-magnetic conductive layer 19ij The bit wiring BLi (i=1 to 4) is provided corresponding to each row of the memory units 10Aij, and the memory units 10Aij of each row share the bit wiring BLi. Further, the gate electrode portion SGj (j=1 to 4) of the vertical thin film transistor 18ij is shared by the memory units 10Aij of each row as in the case of the first embodiment shown in
Further, the field line FLj is provided corresponding to each memory unit 10Aij (j=1 to 4). Each field line FLj (j=1 to 4) is disposed between the flange portion 12fij of the magnetic member 12ij of the corresponding memory unit 10Aij and the yoke 50.
When information is written to the memory unit 10Aij (j=1 to 4) configured in this way, it is performed by supplying the write current by the control circuit 100 to the corresponding field line FLj. The shift operation that shifts the written information and the read operation of the information are performed in the same manner as in the method described in the first embodiment.
In the modification example also, as in the first embodiment, since the write is performed such that the information is collectively written to the memory units 10Aij arranged along the field line FLj, an increase in write energy consumption per bit can be prevented.
In the magnetic memory of the modification example configured in this way, as in the first embodiment, since in the magnetic member 12ij (j=1 to 4), the first end portion 12aij is electrically coupled to the magnetoresistive element 14ij and the second end portion 12bij is electrically coupled to the plate electrode PL, it is possible to highly integrate the magnetic member 12ij. In the present embodiment, the vertical thin film transistor 1811 is used as a selection element that selects the memory unit 10Aij (j=1 to 4). Accordingly, as compared with a case where a two-terminal switching element is used as the selection element, the hold current required for the switching element becomes unnecessary, and the margin between the read current value and the shift current value can be expanded.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
Number | Date | Country | Kind |
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2021-144303 | Sep 2021 | JP | national |