Claims
- 1. A magnetoresistive memory, comprising:
a cell array having a matrix formed of leads including column leads and row leads and a multiplicity of magnetic memory cells disposed at crossover points of said column leads and said row leads, said magnetic memory cells connected to said column leads and said row leads for conducting read currents and write currents, in an event of a write operation, magnetic fields generated by the write currents in said leads are added at a random crossover point and thereby enable a magnetization reverse of said magnetic memory cell, said leads having a form optimized by deviating from a square cross section thereof in such a way that a magnetic field component lying in a cell array plane decreases sufficiently rapidly with increasing distance from a respective crossover point.
- 2. The magnetoresistive memory according to claim 1, wherein said leads have a flat rectangular cross-sectional shape.
- 3. The magnetoresistive memory according to claim 2, wherein said flat rectangular cross-sectional shape has a width at least three times greater than a given height.
- 4. The magnetoresistive memory according to claim 2, wherein said leads have a laterally beveled rectangular cross-sectional shape.
- 5. A magnetoresistive memory circuit, comprising:
a semiconductor substrate; a magnetoresistive memory disposed on said semiconductor substrate, said magnetoresistive memory containing a cell array having a matrix formed of leads including column leads and row leads and a multiplicity of magnetic memory cells disposed at crossover points of said column leads and said row leads, said magnetic memory cells connected to said column leads and said row leads for conducting read currents and write currents, in an event of a write operation, magnetic fields generated by the write currents in said leads are added at a random crossover point and thereby enable a magnetization reverse of said magnetic memory cell, said leads having a form optimized by deviating from a square cross section thereof in such a way that a magnetic field component lying in a cell array plane decreases sufficiently rapidly with increasing distance from a respective crossover point; and a circuit for generating the read currents and the write currents integrated in said semiconductor substrate, said circuit having an interconnect system and said leads integrated into said interconnect system.
Priority Claims (1)
Number |
Date |
Country |
Kind |
100 55 936.0 |
Nov 2000 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of copending International Application No. PCT/EP01/12622, filed Oct. 31, 2001, which designated the United States and was not published in English.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/EP01/12622 |
Oct 2001 |
US |
Child |
10436428 |
May 2003 |
US |