This application relates to main spacer trim-back film and, more particularly, to main spacer trim-back for replacement gate process.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. Such advances have increased the complexity and challenges of processing and manufacturing of ICs.
In IC manufacturing, spacers are formed on the sidewalls of gate stacks. Spacers are needed to isolate the gate stacks from neighboring silicide regions. However, spacers make the spaces between gate stacks become narrower. As technology advances, the distance (or space) between gate stacks become smaller and the aspect ratios of such space become higher. The small distance and high aspect ratio of the space between neighboring gate stacks degrade the quality of silicide formed between the neighboring gate stacks, which results in high resistivity and poor contact yield.
Based on the problems described above, there is a need for processes that would increase the distance between adjacent gate stacks to improve silicide quality and to improve contact yield.
The embodiments of methods described below for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etch-back (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. Silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.
In one embodiment, a method of trimming back main nitride spacers of replacement gate structures on a substrate is provided. The method includes an operation of forming main nitride spacers for replacement gate structures on the substrate. The replacement gate structures have a high dielectric constant (high-K) dielectric layer and a dummy polysilicon layer over the high-K dielectric layer, and a hard mask with an oxide layer over a nitride layer. The method also includes an operation of performing source and drain implants. Source and drain patterns are formed to allow source and drain implants to be performed on desired regions of the substrate and the source and drain patterns are removed from the substrate after the source and drain implants are performed. The method further includes an operation of trimming back the main nitride spacers to increase a space between two adjacent replacement gate structures on the substrate to allow proper formation of metal silicide by subsequent processing and to increase contact yield. Additionally, the method includes an operation of performing source and drain anneal, and an operation of forming the metal silicide on the substrate.
In another embodiment, a method of trimming back main nitride spacers of replacement gate structures on a substrate is provided. The method includes an operation of forming main nitride spacers for replacement gate structures on the substrate. The replacement gate structures have a high dielectric constant (high-K) dielectric layer and a dummy polysilicon layer over the high-K dielectric layer, and a hard mask with an oxide layer over a nitride layer. The method also includes an operation of performing source and drain implants. Source and drain patterns are formed to allow source and drain implants to be performed on desired regions of the substrate and the source and drain patterns are removed from the substrate after the source and drain implants are performed. The method further includes an operation of performing first trim-back of the main nitride spacers to increase a space between two adjacent replacement gate structures on the substrate to allow proper formation of metal silicide by subsequent processing and to increase contact yield, and an operation of performing source and drain anneal. In addition, the method includes an operation of implanting polysilicon on the substrate before the forming of the metal silicide. The implanted polysilicon improves the quality of the metal silicide formed. The first trim-back of the main nitride spacers reduces shadowing effect of polysilicon implant, and an operation of forming the metal silicide on the substrate. Additionally, the method includes an operation of performing second trim-back of the main nitride spacers to increase the space between two adjacent replacement gate structures on the substrate to further increase the contact yield.
In yet another embodiment, a method of trimming back main nitride spacers of replacement gate structures on a substrate is provided. The method includes an operation of forming main nitride spacers for replacement gate structures on the substrate. The replacement gate structures have a high dielectric constant (high-K) dielectric layer and a dummy polysilicon layer over the high-K dielectric layer, and a hard mask with an oxide layer over a nitride layer. The method also includes an operation of performing source and drain implants. Source and drain patterns are formed to allow source and drain implants to be performed on desired regions of the substrate and the source and drain patterns are removed from the substrate after the source and drain implants are performed. The method further includes an operation of performing first trim-back of the main nitride spacers to increase a space between two adjacent replacement gate structures on the substrate to allow proper formation of metal silicide by subsequent processing and to increase contact yield, and an operation of performing source and drain anneal. In addition, the method includes an operation of forming the metal silicide on the substrate, and an operation of performing second trim-back of the main nitride spacers to increase the space between two adjacent replacement gate structures on the substrate to further increase the contact yield.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
The present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements.
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
In one embodiment, the sidewalls of gate stacks 103a, 103b are protected by a seal layer 104, which is made of one or more dielectric materials. In one embodiment, the seal layer 104 is made of a composite layer of oxide and nitride. The seal layer 104 is used to isolate the materials in the gate stacks from the processing environment. For example, the seal layer is about 4-5 nm. However, in some embodiments, the seal layer 104 is not needed. The gate stacks 103a, 103b are surrounded by spacers, which are made of dielectric material(s). Spacers are used to isolate the gate dielectric layer from the surrounding salicide regions 109a, 109b, 109c, and contacts to prevent leakage and shorting. Spacers can be made of a single layer (only main nitride spacer layer), or of multiple layers. The embodiment shown in
The gate stacks 103a, 103b are covered by a nitride etch stop layer 108, which extends to substrate surface that are not covered by the gate stacks 103a, 103b and contact hole 102. Between the gate stacks 103a, 103b, there is a silicide region 109c, which may also exist in other part of substrate, such as region 109a and 109b. The contact plug 102 may be filled with an adhesion (or barrier) layer 111 and a metallic material 112, such as tungsten (W). The contact plug 102 lands on the silicide region 109 and is surrounded by a dielectric material 110.
For advanced processing technologies, the space “D” between two adjacent gate structures such as 101a, 101b may be 0.25 μm or lower, and the aspect ratio of such space may be equal to or greater than 1.5. The decreasing dimension of space “D” and increasing of aspect ratio make the silicide formation in regions, such as 109a, 109b, and 109c, more difficult because it's harder for silicide metal to be deposited in the space. Further, advanced salicide formation often involves implant of polysilicon on the silicide metal to improve the quality of silicide. The decreasing space “D” increases the aspect ratio between two adjacent gate structures and prevents the polysilicon from reaching the surface of region 109c. If metal silicide is not formed properly, the resistance of the silicide can be very high, which can impact contact yield. In addition, the tight spacing makes the patterning and landing of the contact plug 102 more challenging. For example, the limited spacing can make contact hole in region 109c not open or not open completely. The limited spacing can also affect the gap-fill of the contact plug 102. Without sufficient landing area for contact plugs, such as plug 102, the resistance of interconnect can be very high. All these issues can decrease contact yield.
Main spacers 107 are used to isolate the gate dielectric 120 from the surrounding conductive areas, such as silicide regions and contact plugs. About 50 Å (angstroms) of main nitride spacers is required to ensure that there is no leakage between gate dielectric 130 and contact 112, or between gate dielectric 130 and silicide region 109c. During spacer formation, thicker nitride film, such as about 200 Å to about 3000 Å, is deposited to ensure sufficient nitride coverage across the entire substrate. The deposited nitride layer is then etched back to form main spacers 107. For example, the average thickness of the main nitride spacer may be between about 25 nm to about 40 nm. Sufficient thickness of the main nitride spacers is needed to allow source and implant to be performed at relatively high dosage and energy. After source and drain implant, the spacers can be trimmed (or etched) to be thinner to increase the distance of space “D” to improve silicide (or salicide) quality and to improve contact yield.
After the main spacers 237 are formed, source and drain (or S/D) implants are performed at operation 202. The operation 202 includes patterning to define regions for S/D implants. In one embodiment, the source and drain implant includes additional electrostatic source and drain implant. Afterwards, source and drain (S/D) anneal is performed at operation 203. The annealing the substrate to drive dopants in the source and drain regions into the substrate, wherein the protective oxide layer is deposited on the substrate before the substrate is annealed to prevent boron out-gassing. In one embodiment, operation 203 includes depositing a protective oxide layer to protect the boron in the S/D regions from out-gassing during source/drain anneal. The protective oxide layer does not have to be very thick. For example, the thickness of the protective oxide layer can be between about 100 Å to about 500 Å.
After operation 204, a polysilicon implant is performed at operation 205. The polysilicon implant allows the silicon surface to be covered by polysilicon, which improves the silicide quality when the silicide is formed by subsequent processing. One key challenge in developing a salicide (or silicide) process is controlling the specific phase (or compound) formed by the silicide-metal/silicon reaction. Implanted polysilicon on the silicon surface improves the quality (or compound, or phase) of metal silicide formed. As mentioned earlier, the wider distance of “D*′” allows more polysilicon to reach the silicon surface in tight spaces, such as between two adjacent gate stacks. However, the trim-back of main nitride spacers cannot be too extensive to prevent silicide encroachment when silicide is formed later. Sufficient thickness of the main nitride spacers is needed to prevent silicide encroachment.
After polysilicon is implanted, the process flow continues to silicide formation at operation 206. The operation of silicide formation includes the deposition of silicide metal and thermal annealing following the metal deposition. Examples of transitional metals used in salicide technology include titanium, cobalt, nickel, platinum, and tungsten. The thermal anneal can be a rapid thermal annealing, which allows the silicide metal, such as Ni, to form metal silicide with silicon and polysilicon on the substrate surface. The operation of silicide formation can further include a main nitride etching process to reduce the thickness of main nitride spacers, to increase the distance between two adjacent gate structures, and to reduce the aspect ratio(s) between two adjacent gate structures.
After silicide is formed, additional process operations are performed to form contact plug at operation 207. The operation may include depositing a contact etch stop layer under the pre-metal dielectric layer.
By trimming back the main nitride spacers, there is more room for silicide metal, such as Ni, to be deposited in the small silicide regions, such as region 239c. Further, the more opened spacing for the silicide region 239c also allow sufficient polysilicon to be implanted in the silicide region (or salicide region) 239c without being affected by the shadowing effect of the neighboring gate stacks 250a, 250b. In addition, as described above in
The method described above applies for gate stacks formed by poly gate on oxide or oxynitride dielectric (or conventional gate-first structure). However, when such method is applied on replacement gate devices, problems arise.
In order to perform trim-back for main nitride spacers, the trim-back process needs to be performed before the removal of hard-mask layers.
At operation 401, main nitride spacers are formed to surround the gate stacks.
After the main spacers 437 are formed, source and drain (or S/D) implants are performed at operation 402. Operation 402 is similar to operation 202 described above and includes patterning to define regions for S/D implants. Instead of performing S/D anneal next (as in the process flow of
After the thin oxide layer 441 is removed, the nitride spacers are trimmed back by nitride etching chemistry(ies). The nitride etching chemistry(ies) yes can be a wet process, a dry process, or a combination of wet and dry processes. An example of a wet nitride etch process utilizes phosphorous acid (H3PO4) at about 120° C. The etching time depends how much nitride is to be removed. For example, the etching time is between about 1 minute to about 3 minutes. As mentioned above, the trim-back of main nitride spacers cannot be too extensive to prevent silicide encroachment when silicide is formed later. Sufficient thickness of the main nitride spacers is needed to prevent silicide encroachment.
After main nitride spacer trim-back, source and drain anneal is performed at operation 404. Operation 404 is similar to operation 203 described above. Operation 404 is followed by operation 405, which implants polysilicon to improve silicide quality. Operation 405 is similar to operation 205 described above. Silicide is formed afterwards at operation 406. The operation of silicide formation includes the deposition of silicide metal and thermal annealing following the metal deposition. Examples of transitional metals used in salicide technology include titanium, cobalt, nickel, platinum, and tungsten. The thermal anneal can be a rapid thermal annealing, which allows the silicide metal, such as Ni, to form metal silicide with silicon and polysilicon on the substrate surface.
After silicide formation, there is an optional operation 407. At operation 407, the main nitride spacers are further etched to increase the distance between two adjacent gate structures, and to reduce the aspect ratio(s) between two adjacent gate structures. The etching process can be wet, or dry, or a combination of both. For example, a wet nitride etching process utilizing H3PO4 at 120° C. can be applied for a duration between about 1 minute to about 5 minutes.
Since the nitride spacers have been trimmed back, the spacing between the two gate structures is bigger and the aspect ratio of the space is lower to allow better silicide metal deposition (better step coverage) and better pre-silicide-formation polysilicon implant (less shadowing effect). Better silicide metal deposition and better polysilicon implant would result in improved (or better) formation of metal silicide. Also as mentioned above, the wider spacing between the two gate structures also allows contact to form a and land better, and increases contact yield.
The process sequence (or method) mentioned above for trimming back nitride spacers for replacement gates allows the hard mask layers to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. As mentioned above, the minimal main nitride spacer thickness should be controlled to be about 50 Å. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The process also allows widening the space between the gate structures and lowering the aspect ratio of such space to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.
Various modifications, changes, and variations apparent to those of skill in the art may be made in the arrangement, operation, and details of the methods and systems disclosed. Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.