Patent Application
20080222365
Managed memory modules are gaining wide use in a variety of different applications. Managed memory modules are memory modules that employ a dedicated memory controller that performs at least a portion of the memory management functions for the memory device on the memory module. For example, the memory controller can manage access to the memory devices, handle error correction, wear leveling, bad block management, and other administrative tasks for the memory devices.
Managed memory devices are now supplanting earlier-used memory and disk drive technologies in many processor-based systems, such as wireless phones and computers. In these devices, a separate boot memory is often directly connected to the processor to store boot code for the processor (including protocols/drivers for the memory controller). Eliminating this separate boot memory by consolidating the boot code into the memory devices would be desirable.
A managed memory system is provided. More specifically, in one embodiment, a system includes a memory device and switch coupled to the memory device. The switch has at least a first switch position and a second switch position. The system also includes a memory controller coupled to the first switch position and a processor interface coupled to the second switch position.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below.
Like reference symbols in the various drawings indicate like elements.
The coupled controller includes a managed interface, a processor interface, and a switch that is coupled to the managed interface and the processor interface. The switch is configured to switch control of the one or more memory devices between the controller and a processor coupled to the processor interface.
With reference to
The illustrated exemplar system 10 includes a processor 12 coupled to a memory module 14. Processor 12 may include any suitable form of processing unit. For example, in various configurations, processor 12 may include a central processing unit (“CPU”), a microprocessor, an application specific integrated circuit (“ASIC”), a field-programmable gate array (“FPGA”), or another suitable logic device. Processor 12 will typically have a raw memory interface from which it can boot.
In the illustrated example, processor 12 is coupled to memory module 14 through a managed interface 16 and a processor interface 18 within memory module 14. Managed interface 16 may be any of a variety of suitable interfaces for processing communications between processor 12 and a memory controller 20. Processor interface 18 may be an interface suitable for processing communications between processor 12 and memory devices. Processor interface 18 may provide the electrical and protocol equivalent of a raw memory interface from which processor 12 typically boots. Conversely, memory controller 20 provides managed interface 16 with support for a higher-level protocol that is typically error corrected, wear leveled, and bad-block corrected.
For example, in one configuration, processor interface 18 is a NAND flash memory interface provided by memory devices 22a and 22b. In an alternate example configuration, processor interface 18 includes an INTEL firmware hub (“FWH”) that permits direct booting of an X86 based processors through processor interface 18. As will be described further below, managed interface 16 may be used by processor 12 for memory requests that are to be handled by memory controller 20; whereas processor interface 18 is used for direct memory accesses by processor 12.
Although managed interface 16 and processor interface 18 are illustrated in
Memory controller 20 may be any type of memory controller suitable to manage memory devices 22a and 22b. For example, memory controller 20 may, for example, be implemented with a multimedia card (“MMC”) controller, a secure digital (“SD”) controller, an AT attachment (“ATA”) controller, a serial ATA controller, a FLASH memory controller (either NOR or NAND), a serial FLASH controller, such as a serial peripheral interface (“SPI”) controller, and so forth. The above-listing of suitable memory controllers 20 is not intended to be exclusive.
Memory controller 20 is configured to receive memory access requests, such as READS and WRITES, from processor 12 over managed interface 16. Upon receiving a memory access request, memory controller 20 accesses memory device 22a or 22b associated with the memory request and performs the appropriate memory access (e.g., reading data from one or more of the memory devices 22a or 22b or writing data to one of the memory devices 22a or 22b). If the memory access was a read, memory controller 20 will then transmit the read data to processor 12, and if the memory access was a write, memory controller 20 may transmit a write status to processor 12 (e.g., success, failure, etc.).
In addition to handling memory access requests for processor 12, memory controller 20 may also be configured to manage the operation and use of memory devices 22a or 22b. For example, memory controller 20 can be configured to provide error correction functionality to memory devices 22a or 22b. Memory controller 20 may also be configured to remap memory blocks within memory devices 22a or 22b to spread write operations between the various sectors of memory devices 22a or 22b to promote even wear between the various sectors of memory devices 22a or 22b. This remapping is known as wear leveling. Memory controller 20 may also be configured to perform bad block management techniques that identify and avoid bad blocks within memory devices 22a or 22b. Moreover, memory controller 20 may also perform additional management functions for memory devices 22a or 22b.
Memory devices 22a or 22b may include any suitable type of semiconductor memory. In some configurations, memory devices 22a or 22b include NAND Flash memory. However, in other configurations, memory devices 22a or 22b include other suitable types of Flash memory, volatile memory, or non-volatile memory.
As shown in the example system of
Memory module 14 may also include an extension interface 26. Extension interface 26 is coupled to the same interfaces in the managed memory module as memory devices 22a or 22b and enables additional memory devices to be coupled to memory module 14 to increase the memory capacity of memory module 14. In some embodiments, memory module 14 includes multiple flash busses with flash memory devices attached to each bus. The use of multiple flash busses connected to the managed memory controller 20 provides for parallel transfers at a rate exceeding the capabilities of a single memory device 22a or 22b.
The extension interface 26 typically provides the electrical and protocol functions expected by a memory device 22a or 22b. These signals are duplicated by the number of parallel busses provided by the controller 20, which can typically be two or more (not shown). The extension interface 26 also may include chip select signals to allow selection of individual memory parts placed on a system board outside the memory module 14.
As described above, systems 10 and 40 can be configured to switch access and control over memory devices 22a or 22b between processor 12 and memory controller 20 (via switch 24). Advantageously, in some configurations, this functionality may enable boot code for processor 12 to be stored on one or more of the memory devices 22a or 22b while, at the same time, enabling memory controller 20 to manage memory devices 22a or 22b during normal operations of system 10, for example. In particular, switch 24 may directly connect processor 12 to memory 22a at the start of boot-up sequence and then switch to connecting memory controller 2 and memory 22a later in the boot-up sequence. This functionality may relieve the requirement for a separate boot memory for processor 12, thus, potentially reducing the complexity and/or cost of system 10, for example.
Next, the processor may read boot code from a memory device over a processor interface, as indicated by block 64. For example, processor 12 may read row zero from memory device 22a over processor interface 18. Alternatively, the processor may be configured to read the boot code from any other suitable memory location within the memory devices 22a or 22b. As indicated by
After reading the boot code, the processor may boot using the boot code, as indicated by block 66. At some point during the boot process, the processor will load a memory controller protocol from the memory device and initialize a memory controller, such as memory controller 20. After initializing the memory controller, the processor may access the memory controller and, thus, the memory device through managed interface, as indicated by block 70.
When the memory controller detects the memory request for the memory devices being received through the managed interface, the memory controller or another suitable control system may shift the position of the switch to connect the memory device to the memory controller, as indicated by block 72. In some embodiments, the position of the switch may alternatively be shifted when the memory controller is initialized. After the switch has connected the memory controller to the memory devices, future memory requests are processed through the memory controller (e.g., through managed interface 16), as indicated by block 74.
There are also provided methods and techniques for assembling some or all of the system 10 or the system 40. For example, in one embodiment, there is provided a method of manufacturing a memory module, the method including providing a memory device and coupling the controller to the memory device, wherein the controller has a managed interface, a processor interface, and a switch coupled to the managed interface and the processor interface. The switch in this technique is configured to switch a connection to the memory device between the managed interface and the processor interface. This technique may also include coupling the processor interface to the processor and coupling the managed interface to the processor.
In another embodiment, there is provided a technique for manufacturing a memory module that includes providing a memory device, coupling the memory device to a switch having at least a first switch position and a second switch position, coupling a memory controller to the first switch position, and coupling a processor interface coupled to the second switch position.
It will be seen by those skilled in the art that many embodiments taking a variety of specific forms and reflecting changes, substitutions, and alternations can be made without departing from the spirit and scope of the invention. Therefore, the described embodiments illustrate but do not restrict the scope of the claims.
