Patent Application
20230155010
This disclosure relates article of manufacture and method of forming the article of manufacture where the article of manufacture is a bipolar-junction transistor having a photonic platform and including one or more base portions, one or more collector portions, and one or more emitter portions that are all in contact with a dielectric, a semiconductor, or both that form a substrate.
Photonic integrated circuits (PICs) often include optical waveguides for transporting optical waves around a device and into and out of various photonic structures. A waveguide is a structure that confines and guides the propagation of an electromagnetic wave. Some electromagnetic waves have a spectrum that has a peak wavelength that falls in a particular range of optical wavelengths (e.g., between about 100 nm to about 1 mm, or some subrange thereof), also referred to as “optical waves,” “light waves,” or simply “light,” and waveguides for light will be referred to herein as “optical waveguides.” These optical waveguides may be implemented, for example, by forming a core structure from a material having a higher refractive index (e.g., silicon, or silicon nitride) surrounded by a cladding (also called a “buffer”) comprising one or more materials (or air) that have a lower refractive index. For example, the core structure may be formed by the silicon layer over a buried oxide (BOX) layer (e.g., silicon dioxide) of a substrate, such as a silicon-on-insulator (SOI) wafer, while the cladding would be formed by the oxide of the BOX layer and the silicon dioxide deposited on top of the core structure.
In one aspect, in general, an article of manufacture, having a semiconductor layer and a dielectric layer. The semiconductor layer comprising a first surface and a second surface. The dielectric layer located adjacent to the first surface of the semiconductor layer. One or more base portions of the semiconductor in direct contact with and extending from the dielectric layer. One or more collector portions of the semiconductor in direct contact with and extending from the dielectric layer. One or more emitter portions of the semiconductor in direct contact with and extending from the dielectric layer. The one or more collector portions are spaced apart from the one or more emitter portions by the one or more base portions.
In another aspect, in general, a method including etching, doping, and forming. Etching and doping all or a portion of a semiconductor layer to form an emitter portion directly on a dielectric layer. Etching and doping all or a portion of the semiconductor layer to form a base portion directly on the dielectric layer. Etching and doping all or a portion of the semiconductor layer to form a collector portion directly on the dielectric layer, wherein the collector portion and the emitter portion are separated by the base portion. Forming a first metal contact structure within a via pattern in the dielectric layer to form an emitter contact directly on the semiconductor. Forming a first metal contact structure within a via pattern in the dielectric layer to form a base contact directly on the semiconductor. Forming a first metal contact structure within a via pattern in the dielectric layer to form a collector contact directly on the semiconductor.
Aspects can have one or more of the following advantages.
Typical photonic platforms, such as CMOS-compatible SOI platform includes electronic devices such as photodetectors, but are not typically used for certain kinds of electronic devices such as bipolar junction transistors (BJTs). In some cases, BJTs are built layer by layer on a substrate such that one layer is stacked upon another layer. But, it may be advantageous to instead build BJT portions extending from a common dielectric layer, such as a BOX layer in an SOI platform. Implementations of various techniques described herein enable BJTs to be integrated into a photonics platform, such as a CMOS-compatible SOI platform, with certain advantageous characteristics. For example, it may be desirable to have a BJT that has a small base surface area, an emitter portion with limited contact with the base, and/or a BJT with a low series resistance.
Other features and advantages will become apparent from the following description, and from the figures and claims.
The disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to-scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity.
The base portion 106 mediates flow between the emitter portion 110 and the collector portion 108. The base portion 106 is located between the emitter portion 110 and the collector portion 108. The base portion 106 may extend orthogonal to a substrate (e.g., a semiconductor or a dielectric). The base portion 106 may extend in a direction parallel to the emitter portion 110 and the collector portion 108. The base portion 106, collector portion 108, and emitter portion 110 may all be in communication with a common substrate (not shown). The base portion 106 may include metal. The base portion 106 may be doped. The base portion 106 may have a different doping, a lower doping, an opposite doping, or a combination thereof than the collector portion 108, the emitter portion 110, or both. The base portion 106 may be a p-type. The base portion 106 may be positively doped. The base portion 106 may be a n-type. The base portion 106 may be negatively doped. The base portion 106 may have a doping strength such that the doping strength may be a p-type, Pp-type (also known as P+), Ppp-type (also known as P++) doping, or a combination thereof (NPN type), or may be a n-type, Np-type (also known as N+), Npp-type (also known as P++) doping, or a combination thereof (PNP type). The base portion 106 may be doped more than the collector portion 108. The base portion may be doped less than the emitter portion 110. The base portion 106 may allow current to extend from the emitter portion 110 to the collector portion 108. The base portion 108 may be thinner than the collector portion 108 and the emitter portion 110.
The collector portion 108 may collect electrons or collect holes (e.g., a reverse flow of electrons causes mobile holes to be formed). The collector portion 108 functions to receive holes, electrons, or both from the emitter portion 110. The collector portion 108 may be the least doped portion (e.g., doped less than the base portion 106 and the emitter portion 110). The collector portion 108 may be positively doped. The collector portion 108 may be a p-type. The collector portion 108 may be a n-type. The doping strength may be varied such as Np-type (also known as N+) or Npp-type (also known as N++). The collector portion 108 and the emitter portion 110 may be doped the same way. The collector portion 108, the emitter portion 110, or both may be doped opposite the base portion 106.
The emitter portion 110 may emit electrons or holes. The emitter portion 110 may pass electrons or holes through the base portion 108 into the collector portion 106. The emitter portion 110 may be the highest doped portion. The emitter portion 110 may be positively doped. The emitter portion 110 may be a p-type, Pp-type, Ppp-type, or a combination thereof. The emitter portion 110 may be negatively doped. The emitter portion 110 may be a n-type, Np-type, Npp-type, or a combination thereof. The collector portion 108 and the emitter portion 110 may be doped the same way. The collector portion 108, the emitter portion 110, or both may be doped opposite the base portion 106.
Doping a material such as silicon can be accomplished as part of a fabrication process by introducing atoms of a foreign material (also called “impurities”), which can be of two different types: a n-type dopant (which provides free electrons as negative charge carriers (e.g., donor)), or a p-type dopant (which provides mobile holes as positive charge carriers (e.g., acceptor)). Examples of p-type dopants include boron, gallium, or aluminum. Examples of n-type dopants include arsenic, phosphorous, or antimony. The concentration of a dopant can be characterized by different degrees of concentration, which can be associated with corresponding symbols (P for p-type, and N for n-type) within various quantitative ranges. A “P” or “N” designation of concentration is a moderate degree of doping (e.g., a concentration of less than 1018 atoms per cubic centimeter). A doping strength of “P+” or “N+” designation of concentration (also referred to herein as “Pp” or “Np”) is a heavy degree of doping (e.g., a concentration of between about 1018 to 1020 atoms per cubic centimeter). A “P++” or “N++” designation of doping strength or doping concentration (also referred to herein as “Ppp” or “Npp”) is an even heavier degree of doping (e.g., a concentration of greater than about 1020 atoms per cubic centimeter). Dopant concentration may vary vertically across a cross-section according to implantation energy.
An area under metal contact structure 112 may be partially doped such that a portion is doped to form a contact to facilitate an electrical connection. The doping that is adjacent and under the metal contact structure 112 may form an ohmic contact. The area under the contacts may be fully doped to facilitate a flow of electrons. An amount of doping adjacent the metal contact structure 112 may vary an amount of resistance. The metal contact structure 112 may be connected to a circuit or may connect the AOM 100 within a circuit.
The dielectric 104 may be any material that has high capacitance, prevents electrical leakage, insulates the semiconductor, or a combination thereof. The dielectric 104 may have a thermal conductivity of about 5 W/(m*K) or less, about 3 W/(m*K) or less, about 1.5 W/(m*K) or less (e.g., about 1.4 W/(m*K)). The dielectric 104 may be or include silicon, silicone dioxide, porcelain, mica, glass, or a combination thereof. The dielectric 104 may be a buried oxide layer (BOX). The dielectric 104 may be a continuous layer. The semiconductor 102 may include metallization on top of it or may be etched. The metallization may be formed after oxide 124 is deposited, by patterning a via in such a layer and filling it with metal.
The dielectric 104 may separate the semiconductor 106 from the semiconductor 102. The dielectric 104 may be free of extending between the any of the base portion 106, the collector portion 108, and the emitter portion 110.
A metal contact structure 120 and metal contact layer 122 may be located within the oxide 124 above the semiconductor 102 and be in electrical contact with the base portion 106, the collector portion 108, or the emitter portion 110. The metal contact structures 112 may be configured to include metal layer 122 and vias 120 that form an electrical connection to portions of the AOM 100 (although only one surface contact and via structure is being shown for clarity of the figure). The metal contact structures 112, including the vias 120, all or a portion of the metal layer 122, or a combination thereof may be located within oxide 124. The metal contact structures may be located above the dielectric 104, on an oxide layer 124, or both. The metal contract structures may be free of contact with the semiconductor 102. The metal contract structures may be located in a via pattern of an oxide.
The semiconductor 118 (e.g., doped semiconductor 118), a region surrounding the metal contact structures, or both are doped forming the base portion 106, the collector portion 108, and the emitter portion 110. Semiconductor 118 may be etched to a specific height from an unprocessed SOI wafer containing semiconductor 102, dielectric 104, and semiconductor 118. The base portion 106, the collector portion 108, and the emitter portion 110 may be etched at different depths. Each of the base portion 106, the collector portion 108, and the emitter portion 110 are directly in contact with and extend away from the dielectric 104. As shown, the base portion 106, the collector portion 108, and the emitter portion 110 all extend generally parallel to one another. The base portion 106, the collector portion 108, and the emitter portion 110 all connect to a same substrate (e.g., the dielectric 104, itself on top of semiconductor 102). The collector portion 108 may be free of the emitter portion 110, the base portion 106, or both extending over all or a portion thereof. For example, an upper most surface, a bottom most surface, or both of the emitter portion 110, the collector portion 108, the base portion 106, or a combination thereof may be free of any overlap by another portion.
The base portion 106, the collector portion 108, and the emitter portion 110 may all be sandwiched together. The base portion 106, the collector portion 108, and the emitter portion 110 all may be formed in parallel, in series, or both. As shown, when viewing
The base portion 106, the collector portion 108, the emitter portion 110, or a combination thereof may be in direct communication with a via 120 (e.g., formed from a conductive material, such as metal). The via 120 may create an electrical connection with a metal layer 122 so that current may exit or enter the article of manufacture. An oxide 124 may extend over all or a portion of the base portion 106, the collector portion 108, the emitter portion 110, the vias 120, the surface contacts 122, or a combination thereof. The oxide 124 may encapsulate one or more of the layers discussed herein. The oxide layer may be an undoped silicate glass (USG).
The cross-sectional view of
The present AOM may be created by a method of manufacture. The semiconductor may be formed. The semiconductor may be etched. The method of manufacture may include depositing a dielectric on the semiconductor. Forming via patterns in the dielectric by removing portions of the dielectric, selectively etching the dielectric, masking the semiconductor so that dielectric is applied to the mask and when the mask is removed the semiconductor is exposed, or a combination thereof. Metal may be placed in the via patterns to form the vias making contact to the doped semiconductor portions at one end of the via. Each via hole may receive one metal via with a metal layer formed at the other end of the via. Three via patterns may be formed, filled with a metal material, and three metal contacts may be formed on a top surface and connected to base, collector, and emitter portions of the AOM 100 by the metal vias. The semiconductor structures connected to the vias and forming the base, collector, and emitter portions may be doped. The doping selected may determine what portion is formed. The doping may form an emitter portion, a collector portion, and a base portion. The doping or doping strength may make a portion positive, negative, neutral, a free electron receptor, a free electron donor, or a combination thereof.
While the disclosure has been described in connection with certain embodiments, it is to be understood that the disclosure is not to be limited to the disclosed embodiments but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures as is permitted under the law.
