Claims
- 1. A method of manufacturing a CMOS transistor, said method comprising the steps of:
- forming gate electrodes of an N-channel transistor and a P-channel transistor on a semiconductor substrate with a gate insulating layer therebetween;
- forming N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor, using the gate electrode of the N-channel transistor as a mask;
- conducting a first thermal treatment to said gate electrodes and said N-type heavily doped diffusion layers at a first temperature of more than approximately 900.degree. C.;
- forming P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor, using the gate electrode of the P-channel transistor as a mask; and
- conducting a second thermal treatment to said P-type heavily doped diffusion layers at a second temperature lower than that of said first thermal treatment.
Parent Case Info
This is a continuation of application Ser. No. 08/443,266, filed May 17, 1995, now U.S. Pat. No. 5,618,748 which is a divisional application of Ser. No. 08/340,375, filed Nov. 14, 1994, now U.S. Pat. No. 5,447,872 which is a divisional application of Ser. No. 08/141,727, filed Oct. 27, 1993, now U.S. Pat. No. 5,409,847.
US Referenced Citations (13)
Divisions (2)
|
Number |
Date |
Country |
Parent |
340375 |
Nov 1994 |
|
Parent |
141727 |
Oct 1993 |
|
Continuations (1)
|
Number |
Date |
Country |
Parent |
443266 |
May 1995 |
|