Patent Application
20240395632
The present disclosure relates to semiconductor devices. Particularly, but not exclusively, the disclosure relates to hetero-structure AlGaN/GaN high electron mobility transistors or rectifiers.
Gallium Nitride (GaN) is a wide band gap material with properties that make it a suitable candidate for use in several fields of application (e.g. radio-frequency electronics, opto-electronics, power electronics) which require solid-state devices.
GaN technology allows transistors with high electron mobility and high saturation velocity to be designed. These properties of GaN have made it a good candidate for high-power and high-temperature microwave applications, for example radar and cellular communications systems.
Additionally, GaN with its wide bandgap offers the potential for emitting light at higher frequencies for example the green, blue, violet, and ultraviolet portions of the electromagnetic spectrum.
Gallium Nitride (GaN) has been more recently considered as a very promising material for use in the field of power devices. The application areas range from portable consumer electronics, solar power inverters, electric vehicles, and power supplies. The wide band gap of the material (Eg=3.39 eV) results in high critical electric field (Ec=3.3 MV/cm) which can lead to the design of devices with a shorter drift region, and therefore lower on-state resistance if compared to a silicon-based device with the same breakdown voltage.
The use of an Aluminium Gallium Nitride (AlGaN)/GaN heterostructure also allows the formation of a two-dimensional electron gas (2DEG) at the hetero-interface where carriers can reach very high mobility (μ=2000 cm2/(Vs)) values. In addition, the piezopolarization charge present at the AlGaN/GaN heterostructure, results in a high electron density in the 2DEG layer (e.g. 1×1013cm−2). These properties allow the development of High Electron Mobility Transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters. One common parameter used to compare power semiconductor transistors is Specific ON-state resistance or Specific Rds(ON). Where specific Rds(ON) is often the product of the resistance of a device times the area of the device on wafer. An extensive amount of research has focused on the development of power devices using AlGaN/GaN heterostructures.
Layers which constitute the AlGaN/GaN heterojunction transistor are often epitaxially grown on a substrate from a different material for example Silicon, Silicon Carbide or Sapphire. Epitaxial growth of GaN on different substrates has advantages and disadvantages both in terms of the difficulty and cost of growing high quality layers and in terms of device performance. A non-exhaustive list of things to consider when choosing a suitable substrate is: substrate lattice constant mismatch with GaN, substrate thermal expansion coefficient mismatch with GaN, substrate cost, substrate thermal conductivity etc.
Silicon is a popular option due to the low cost and availability of Silicon substrates. Use of Silicon as a substrate however comes with some disadvantages. Silicon and GaN have a large lattice constant mismatch and a large thermal coefficient mismatch. A transition layer is used to facilitate the growth of high quality GaN epitaxial layers on Silicon. A transition layer often comprises graded AlN/AlGaN layers or a superlattice. A GaN buffer layer is grown on the transition layer. The GaN buffer layer is often carbon doped to limit vertical leakage from the surface high voltage terminal e.g. drain and the substrate backend contact. An unintentionally doped GaN layer is then grown where the two dimensional electron gas at the interface with an AlGaN barrier layer is present.
Silicon Carbide (SiC) has excellent thermal conductivity (almost three times that of silicon), and therefore GaN-on-SiC is an option which is receiving increasing interest for high power applications. SiC, is also a wide bandgap material which is used to develop power devices. The critical electric field of SiC is comparable to GaN (3.5 MV/cm and 3.3 MV/cm, respectively) and therefore it can also sustain higher voltages in smaller dimensions compared to Silicon. Additionally, SiC has a smaller lattice constant mismatch with GaN compared to Silicon with GaN. Therefore, the growth of epitaxial layers of GaN-on-SiC is less challenging compared to the growth of epitaxial layers of GaN-on-Silicon. GaN-on-Silicon epitaxial growth often comprises a transition layer to manage the stress, warping etc. and achieve high quality material. In GaN-on-SiC, only a thinner AlN nucleation layer is required.
The SiC substrate used in GaN-on-SiC devices may be a monocrystalline 4H-SiC, 6H-SiC or 3C-SiC substrate. The substrate may be doped to be conductive or may be semi-insulating. 4H-SiC is the most commonly available polytype.
Whether the substrate is Si or SiC, in a lateral heterojunction transistor the off-state potential is often sustained both laterally and vertically. Laterally, refers to the dimension between the gate and drain terminal, where gate and drain contacts are both placed on the surface of the wafer. Vertically, refers to the dimension between the drain and substrate contact. The backside of the wafer is often connected to the source potential, often at package level.
The substrate in a GaN device is generally not electrically utilised i.e. it is not used to conduct any current in the normal operation of the device. Additionally, the substrate does not sustain a significant voltage drop across it during the off-state operation of the device. The entire substrate acts as a field plate, virtually taking the substrate potential which is often grounded. In that sense, the substrate may be described as offering a mechanical and thermal function but not necessarily an electrical function in the operation of the device.
As a result, in existing devices the majority or even the entirety of the vertical potential drop is observed in the III-nitride epitaxial layers.
Where a semi-insulating SiC substrate is used, the substrate does have a voltage drop across it. This allows the development of device with thinner GaN-based layers. However, semi-insulating SiC substrates are more expensive and less common than conductive SiC substrates (whether n-doped or p-doped). In addition, the semi-insulating substrate is used in a similar manner to a dielectric material and therefore does not feature or does not behave as an active semiconductor device such as a diode or transistor. There are advantages in using diode or transistors incorporated in the substrate as described as part of this disclosure.
When a monocrystalline doped SiC substrate is used, and it is connected to source potential, the potential drop during the blocking/off-state mode of operation of the HEMT is sustained almost entirely in the Ill-nitride epitaxial layers and in particular a GaN buffer layer. If vertical breakdown is the limiting factor, in order to increase the vertical breakdown of a device, the thickness of the GaN buffer layer is often increased which increases the cost and complexity of epitaxial growth. This also applies to GaN-on-Si devices.
An additional challenge in GaN HEMT is their lack of avalanche capability. Avalanche capability may be beneficial in a power device as it limits the maximum potential that can develop between the high voltage and low voltage terminals of a device, and therefore can limit the maximum electric field in the structure. This may provide reliability advantages, in terms of device lifetime as over-voltages in operation are limited. Because of the lack of avalanche capability, GaN HEMT can often be over engineered in terms of the actual breakdown being much higher than the rated breakdown. This is done by having larger dimensions (e.g. lateral distance between gate and drain and increased thickness of the GaN stack).
Finally, while GaN HEMTs have efficient forward conduction (drain biased positively with respect to source and the gate voltage above the threshold voltage) with low on-state losses, the reverse conduction (when the source and gate potentials are the same and the source is positively biased with respect to the drain) is relatively poor, with significant steady-state losses due to a large drop between the source and drain terminal for a given current level.
US2021/0104623 A1 describes a device including a source electrically coupled to a group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being in the substrate or on the substrate below the group III-nitride barrier layer.
US2021/0167199 A1 describes an apparatus to address gate lag effect and/or other negative performance with a p-region that extends toward a source side of a substrate and towards a drain side of the substrate.
US2022/0344500 A1 describes a high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer.
U.S. Pat. No. 8,390,091 B2 describes a structure that includes a vertical Schottky diode, including an anode; a cathode including the substrate, and a Schottky barrier between the cathode and the anode, the Schottky barrier being situated between the substrate and an anode layer in a stack of layers.
SiC and GaN devices—wide bandgap is not all the same (Kaminski et al), IET Circuits Devices & Systems, 2014, Vol. 8, Iss. 3, pp. 227-236, contains discussions regarding the use of various materials in semiconductor devices.
Design, Fabrication and Characterization of GaN HEMTs for Power Switching Applications (Björn Hult), Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, Chalmers University of Technology, 2022, contains discussions of AlGaN/GaN-on-SiC high voltage metal-insulator semiconductor (MIS) HEMTs fabricated on ‘buffer-free’ heterostructures.
It is an object of this invention to provide a method of forming a wide bandgap transistor on a substrate which features an active high voltage diode. The resulting structure May provide an efficient design leading to a better trade-off between on-state and breakdown, potentially offering avalanche capability as well as an efficient reverse conduction path leading to lower losses during reverse conduction. Part of the diode is placed directly under part of the wide bandgap transistor and is configured to support a substantial fraction of the voltage between the terminals of the power device.
The combination of the wide bandgap transistor and substrate diode may be referred to as a single power device.
The wide bandgap transistor may be formed in a wide bandgap semiconductor.
By wide bandgap, we mean semiconductors with a bandgap of at least 2 eV. Examples of suitable wide bandgap materials include, non-exhaustively, GaN, AlGaN, AlN, GaO, SiC, Diamond, etc.
The wide bandgap transistor may preferably comprise a lateral heterojunction transistor such as a HEMT and the wide bandgap semiconductor may preferably be based on III-Nitride. The wide bandgap semiconductor may comprise a heterojunction between GaN and AlGaN. The substrate may be formed of wide bandgap semiconductor material or low bandgap material such as silicon carbide (SiC such as 4H SiC, 6H SiC or 3C SiC) or Silicon, respectively.
Alternatively, the wide bandgap semiconductor may be made of GaO, AlN, AlGaN and the transistor may be a MOFSET, MESFET, deep depletion FET etc. Alternatively, the semiconductor substrate may be made of GaN, AlN, Diamond.
According to a first aspect of the invention, there is provided a method of making a power device, the method comprising:
In the following descriptions examples of this invention are restricted to a HEMT based on a AlGaN/GaN heterojunction and SiC or Si substrate for improved clarity and readability. However, it will be understood that the invention is more widely applicable to other wide and non-wide bandgap materials as described above.
According to the present disclosure, a method of fabricating a AlGaN/GaN heterojunction device on a SiC/Si substrate is proposed, with a diode in the substrate. The heterojunction transistor can be a HEMT. The HEMT can achieve a more effective potential distribution during the blocking mode (OFF-state bias) or during transients (from low voltages to high voltages or opposite) through a more effective use of the substrate, compared to existing AlGaN/GaN HEMTs. More effective use means that the substrate may be electrically utilised as a high voltage region, by seeing a substantial part of the potential drop between the device drain terminal and the device substrate terminal in the device off-state. This may be achieved through a diode based on a high voltage junction in the substrate layer.
The junction may be part of a p-n diode. Alternatively, a diode based on a p-i-n or p+/p−/n+ or p+/n−/n+ junction, a diode based on a Superjunction or a Schottky diode may be used. Bipolar diodes such as p-n or P-I-N or p+/p−/n+ or n+/p−/p+ junction have lower leakage current and require ohmic metallization. Schottky diodes have relatively higher leakage currents and require at least one non-ohmic, Schottky contact with either the anode or cathode terminal. The Schottky diodes may however feature unipolar conduction in the on-state and this results in very fast switching (generally associated with zero reverse recovery losses if the diode is used in anti-parallel configuration with the HEMT). Combinations of bipolar/Schottky diodes such as Junction Barrier diodes or Merged Schottky-bipolar diodes (also known as Merged p-n Schottky diodes) can also be used.
The incorporation of a diode under at least part of the HEMT device may lead to a design with an improved specific ON-state resistance, as the dimension of the GaN HEMT do not need to be over engineered.
Moreover, the effective use of the substrate as a region can allow substantially thinner GaN-based layers (such as GaN buffer layer or no GaN buffer layer at all). This is advantageous both from a cost perspective and reduced process complexity perspective. Furthermore, since the voltage is laterally distributed within the heterojunction transistor with little or virtually no vertical component, there is less risk of traps being ionized in the GaN buffer which could create reliability issues such as Dynamic Ron increase.
Due to increasing OFF-state bias voltage, impact ionization in the depletion region of the reverse biased diode in the substrate will lead to avalanche breakdown. The reverse biased diode in the substrate may be designed to reach avalanche breakdown before other modes of breakdown in the HEMT (such as soft breakdown due to leakage currents, or static or time-dependent dielectric breakdown) occur in the nitride epitaxial layers or the passivation/dielectric layers in the device, or vertically between the surface terminals and the substrate terminal. Having avalanche capability is highly desirable in some power electronics application. This is because if the surge energy of the device is not exceeded, then an avalanche breakdown is recoverable. On the other hand, other modes of breakdown which may occur in a conventional GaN HEMT, such as dielectric breakdown, are not recoverable.
Depending on the substrate used, the diode in the substrate under the HEMT can also be used in anti-parallel configuration with the GaN HEMT. This may be more suitable in the example where a SiC substrate is used. If a p+/p−/n+ or p+/n−/n+ diodes are used the anode terminal of the diode can be connected to the drain terminal of the HEMT while the cathode terminal of the diode can be connected to the source terminal of the HEMT. If a p+/p−/n+ diode is used the anode terminal may be preferably connected to the backside of the SiC substrate (as the substrate terminal). If a p+/n−/n+ diode is used the cathode terminal for the p+/n−/n+ diode may be preferably connected on the backside of the substrate as the substrate terminal. In either of the two cases mentioned, the SiC diode can be used therefore in a forward-biased mode when the HEMT is in a reverse conduction state. In this configuration, the common source terminal is more positively biased than the drain terminal. In this condition, the SiC diode is forward biased and provides a parallel conduction path to that existing between the source and drain terminals of the HEMT (through the 2DEG layer). The SiC diode can be more effective (offering lower on-state voltage drop or lower equivalent on-state resistance) in the forward-biased mode than the parallel 2DEG channel in a reverse conduction mode thus minimising the on-state losses in this mode of operation. The SiC diode can also take a surge of current. If needed, during this mode of operation. If the SiC diode is largely unipolar and based on a Schottky barrier, then it produces negligible extra charge during reverse conduction and can be very fast during switching leading to very little (negligible) reverse recovery losses.
Furthermore, the parasitic input and output capacitances in the GaN HEMT limit the losses during the transient signals (in particular the turn-on process). By providing a depletion region in the substrate diode under the GaN HEMT, the capacitances (in particular the output capacitance) can be minimised. The large body of the depletion region in the substrate present at higher voltages in the drift region, when the substrate diode is reverse biased directly under the III-nitride semiconductor region leads to a small capacitance, minimising the switching losses and switching time.
Thus, the method of making a power device is provided may comprise:
In one example, the wide-bandgap transistor may be a gallium nitride high electron mobility transistor (GaN HEMT).
In a further example, the GaN HEMT may comprise one or multiple heterojunctions with one or multiple active 2DEG channels, and/or the method may comprise forming multiple GaN HEMTs or other transistors on the substrate. “Active channels” herein refer to the channels that, during ON-state operations of the HEMTs, the current flows through.
Additionally, or alternatively, the method may comprise forming a second heterojunction transistor, for example a second GaN HEMT, over the substrate layer. The second heterojunction transistor may be formed via the same or a different method as the first heterojunction transistor. Further (e.g. third, fourth, etc.) transistors may also be formed. The first and second heterojunction transistors may be connected in a half bridge.
For example, the method may comprise forming a second wide-bandgap semiconductor transistor over the first surface of the substrate layer. Optionally, the wide-bandgap semiconductor transistor and the second wide-bandgap semiconductor transistor may each be high electron mobility transistors (HEMTs). The HEMTs may be connected in a half bridge. In this case, the diode may be a common diode for the HEMTs, or the method may comprise forming a second diode associated with the second wide bandgap transistor. The second diode may be formed in a similar manner to the first diode. For example, at least part of the second diode may located below at least part of the second wide-bandgap semiconductor transistor, the second diode comprising a third terminal and a fourth terminal, the third and the fourth terminal different to the first and second terminals.
In one example, forming a wide-bandgap semiconductor transistor over a first section of the surface of the substrate layer may comprise:
This example of a method of forming a wide bandgap transistor may be more suitable for an AlGaN/GaN HEMT formed on a Silicon substrate or other non-wide bandgap substrate material.
In another example, the method of forming a wide-bandgap transistor may comprise:
This example of a method of forming a wide bandgap transistor may be more suitable for an AlGaN/GaN HEMT formed on a SiC substrate or other wide bandgap substrate material.
In one example, forming a first semiconductor substrate layer doped with at least a first conductivity type may comprise forming a single substrate region which is either p+ doped or n+ doped. The first semiconductor substrate layer may act as an p+ anode layer where an anode contact is formed or may act as a n+ cathode layer where a cathode contact is formed. Alternatively, the single region of the substrate layer may be p− doped or n− doped.
In another example, an additional region doped with a first conductivity type may be formed in the substrate. The additional region may have a low doping concentration (e.g. p− or n−) and may act as a drift region for the high voltage diode associated with the substrate layer. The drift region may be at least partly in physical contact with the III-nitride layers where a GaN HEMT is formed as described in examples above.
The drift region may be formed through diffusion of dopants. Alternatively, it may be formed through an implantation of dopants followed by diffusion.
In another example, an additional substrate region (i.e. second region) doped with a second conductivity type may be formed near the surface of the substrate wafer. The second region may have a higher doping concentration (e.g. n+ or p+) than the drift region. The second region may act as an p+ anode layer where an anode contact is formed or may act as a n+ cathode layer where a cathode contact is formed. This may result in the formation of a vertical p+/p−/n+ or p+/n−/n+ diode, e.g. when a second terminal of the substrate diode is formed on the backside of the wafer (also referred to herein as the opposite side of the substrate layer).
In another example, an additional substrate region (i.e. third region) doped with a first conductivity type of doping may be formed near the surface of the substrate wafer. The third region may have a higher doping concentration (e.g. p+ or n+) than the drift region. The third region may act as an p+ anode layer where an anode contact is formed or may act as a n+ cathode layer where a cathode contact is formed. This may result in the formation of a lateral p+/p−/n+ or p+/n−/n+ diode, e.g. if the first and second terminals of the substrate diode are formed on the surface of the substrate.
In another example, a superjunction region may be formed in the substrate layer. The superjunction may comprise regions of alternating n and p layers, and may act as the drift region for the high voltage diode associated with the substrate layer. The superjunction may comprise a single n+ layer and a single p+ layer, or multiple such layers interleaved with one another. When the superjunction is used as a drift region in a high voltage diode, the n and p layers deplete at high reverse voltages applied between the anode and cathode terminals. The superjunction structure is configured for charge compensation between the n and p layers to provide more uniform electric field and potential distribution during reverse bias.
The layers of the superjunction may be formed such that they alternate vertically or laterally. Laterally herein describes the dimension of separation between the source and drain terminals of the transistor, while vertically (or longitudinally) may describe a perpendicular dimension in which e.g. the gate terminal and substrate are separated.
Part (or the entirety) of the superjunction drift region is physically arranged directly under the active III-Nitride semiconductor regions where the GaN HEMT is formed. The superjunction drift region may be in physical contact with the III-Nitride semiconductor regions where the GaN HEMT is formed.
In one example, the formation of the first terminal of the substrate diode may comprise:
In another example, an ohmic contact may be formed in the recess. In the case where a high doping region (e.g. aforementioned second region) was formed near the surface of the substrate layer, the ohmic contact may be formed on the high doping region. In this case, the alignment of the recess region with the high doping region may be required.
For example, metal contacts may be formed with known processes such as physical vapour deposition (PVD), e-beam PVD, sputtering etc.
In the case where a high doping region was not formed before the growth and recess of the III-nitride layers, a high doping region may be formed after the recess is made (e.g. through implantation of dopants) for a good ohmic contact. The implantation may be self-aligned to the recess region or via a passivation step following the recess.
Following implantation of dopants, a diffusion period may be used.
The formation of the second terminal of the substrate diode may comprise a similar method to any of the examples given for the formation of the first terminal if the second terminal is also formed on the surface of the substrate layer.
In another example, the second terminal of the substrate diode may be formed on the back of the substrate as a back-metallisation contact. A Schottky or ohmic contact may be formed. The contact may be formed for example by physical vapour deposition (PVD) or sintering.
According to a second aspect of the invention, there is provided a method of making a power device comprising:
According to a third aspect of the invention, there is provided a method of making a power device comprising:
In the second and third aspect of the invention, the formation of the terminals of the wide bandgap transistor may need to be appropriately aligned to the second doped region formed in the substrate layer.
The present disclosure will be understood more fully from the accompanying drawings, which however, should not be taken to limit the disclosure to the specific embodiments shown, but are provided for aiding in explanation and understanding only.
Like reference numerals are provided throughout for corresponding features.
In step 100, a semiconductor substrate layer is formed. The semiconductor substrate layer is formed from at least a first doped semiconductor layer with a first conductivity type.
In step 200, a wide-bandgap semiconductor transistor, such as a GaN HEMT or other suitable transistor, is formed over a first section of the surface of the substrate layer. The transistor may be formed directly over the substrate, or additional layers (such as a transition layer) may be provided between the transistor and the substrate. As used herein, a wide bandgap semiconductor material is a semiconductor material with a bandgap of at least 2 eV. Examples of such wide bandgap semiconductor materials include, non-exhaustively, GaN, AlGaN, AlN, GaO, SiC and Diamond.
In step 300, a first terminal is formed on a second section of the surface of the substrate layer. The second section may be laterally separated from the first section along the surface, adjacent to the first section, overlap with the first section or be within the first section.
In step 400, a second terminal is formed. The second terminal may be formed on a “backside” of the substrate layer (e.g. on a second surface of the substrate that is opposite the “top” surface that is facing the transistor), or may be formed on a section of the “top” surface of the substrate layer. As with the second section, the third section may be laterally separated from the first section along the surface, adjacent to the first section, overlap with the first section or be within the first section.
In step 500, the first and the second terminals are configured such that a high voltage diode is formed, wherein a drift region of said high voltage diode is at least partly formed in the substrate layer; and at least part of the diode is directly located under at least part of the wide-bandgap semiconductor transistor; and at least part of the drift region is in physical contact with the wide-bandgap semiconductor transistor.
An electric current flows between the second terminal and the first terminal (or vice versa) when the terminals are biased at an appropriate level. The first and second terminals are therefore formed such that a diode is formed at least partially within the substrate layer. The first and second terminals are located such that at least part of the diode is located below at least part of the wide-bandgap semiconductor transistor and at least part of the diode is in physical contact with at least part of the active region of the wide-bandgap semiconductor transistor. For example, a drift region of the diode may be below the transistor and in physical contact with at least a part of the transistor.
The drift region participates directly to support both laterally and vertically a high voltage or a fraction of the high voltage between the drain terminal of the heterojunction transistor and the anode terminal of the diode, when the heterojunction is in the blocking mode or during the transient states.
It will be understood that the steps of method 1000 may each be sub-divided in additional smaller methods. Further details regarding each of the steps of method 1000, and their various optional embodiments, are provided below.
In a step 201, a III-nitride nucleation layer is formed over the substrate layer.
In a step 202, a transition layer is formed over the nucleation layer.
In a step 203, a III-nitride buffer layer is formed over the transition layer.
In a step 204, a III-nitride channel layer is formed over the buffer layer.
In a step 205, a III-nitride barrier layer is formed over the channel region of the channel layer.
In a step 206, the source terminal and drain terminal of the transistor are configured such that an electric current flows between the source contact and a drain contact via a two-dimensional electron gas (2DEG) induced at a heterojunction interface between the channel layer and the barrier layer when the gate is biased at an appropriate (e.g. threshold) level. The configuration of the source and drain terminals may comprise forming the terminals in a suitable location. This combination of features may therefore form a high electron mobility transistor (HEMT).
An example HEMT formed according to the steps of method 200a is illustrated in
Steps 207-210 correspond to steps 201 and 204-206 of method 200a respectively. However, a transition layer and buffer layer may not be required for a GaN-on-SiC structure. A buffer layer may be included but may be substantially thinner for the same voltage rating compared to a GaN-on-Si structure. Otherwise, the structure may be formed in a similar manner as described for the structure in
Method 1000a comprises method steps 100a, 200a or 200b, 300b, and 400d, and may result in a structure as illustrated in
Method 1000b comprises method steps 100b, 200a or 200b, 300a or 300b, and 400d, and may result in a structure as illustrated in
Method 1000c comprises method steps 100c, 200a or 200b, 300c, and 400d, and may result in a structure as illustrated in
Method 1000d comprises method steps 100d, 200a or 200b, 300c, and 400c, and may result in a structure as illustrated in
Method 1000e comprises method steps 100a, 200a or 200b, 300b or 300c, and 400e, and may result in a structure as illustrated in
It will be understood that the various examples of method steps 100, 200, 300 and 400 described above may be combined in any other arrangement not listed above.
The method may comprise forming a second heterojunction transistor, for example a second GaN HEMT, over the substrate layer. The second heterojunction transistor may be formed via the same or a different method as the first heterojunction transistor. For example, both heterojunction transistors may be formed according to method 1000a, or the first transistor may be formed according to method 1000a while the second heterojunction transistor is formed according to method 1000b. Any other combination may also be used. Further (e.g. third, fourth, etc.) transistors may also be formed. The first and second heterojunction transistors may be connected in a half bridge.
The skilled person will understand that in the preceding description, positional terms such as ‘top’, ‘front’, ‘side’, ‘above’, ‘overlap’, ‘under’, ‘lateral’, etc. are made with reference to conceptual illustrations of a device, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings.
Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.
Many other effective alternatives will occur to the person skilled in the art. It will be understood that the disclosure is not limited to the described embodiments, but encompasses all the modifications which fall within the spirit and scope of the disclosure.
